Intel’s Manufacturing Roadmap from 2019 to 2029
anandtech.com
anandtech.com
They might ship 1.4nm, but it has a good chance of having Soviet tractor quality.
Human capital turnover, market trends, butterflies in Thailand all conspire to foil grand organizational visions.
I wonder if a x86-64 CPU will exceed 1024 cores before the end 2029? It feels like that is where we are headed.
If there's something useful about having 32 32-core chiplets connected to an I/O hub talking to a bunch of PCIe5 lanes and a huge pile of DDR6 RAM, that could happen.
But getting all that compute logic coordinated in one place might not be that economically desirable compared to offloading to GPU-style specialized parallel processors, or building better coordination software to run distributed systems, or...
Fifteen years ago a lot of medium-sized organizations had a full rack of single and dual-core servers in their offices that cost half a million dollars and consumed >10KW of electricity day and night.
That made it attractive to put everything in the cloud -- spend $250K on cloud services instead of $500K on local hardware and you're ahead.
But their loads haven't necessarily changed a lot since then, and we're now at the point where you can replace that whole rack with a single one of these high core count beasts with capacity to spare. Then you're back to having the latency and bandwidth of servers on the same LAN as your users instead of having to go out to the internet, not having to pay for bandwidth (on both ends), not having to maintain a separate network infrastructure for The Cloud that uses different systems and interfaces than the ones you use for your offices, etc.
People might soon figure out that it's now less expensive to buy one local server once every five years.
Then you need someone to plan, provision, troubleshoot, and maintain the physical servers. So at best a full time fully loaded position which costs the company roughly 2x the salary. And that's only if you know your workload so well that you can guarantee the shape of your hardware usage 3-5 years out. Rarely possible in practice.
I'd say always start with the cloud, and you'll know if or when you could do (part) of it cheaper yourself.
That doesn't really change much when the difference is a four figure sum spread over five years.
> Then you need someone to plan, provision, troubleshoot, and maintain the physical servers. So at best a full time fully loaded position which costs the company roughly 2x the salary.
Would it really take a full time position to maintain two physical servers? That's a day or two for initial installation and configuration which gets amortized over the full lifetime, OS updates managed by the same system you need in any case for the guests, maybe an hour a year if you get a power supply or drive failure.
If the maintenance on two physical machines add up to a full week out of the year for the person already maintaining the guests, something has gone terribly wrong. Which itself gets balanced against the time it would take the same person to configure and interact with the cloud vendor's provisioning system -- probably not a huge difference in the time commitment.
> And that's only if you know your workload so well that you can guarantee the shape of your hardware usage 3-5 years out. Rarely possible in practice.
Most companies will do about the same business this year as they did last year plus or minus a few percent, so it's really the common case. And if you unexpectedly grow 200% one year then you use some of that unexpected revenue to buy a third server.
Where the scalability could really help is if you could grow 200,000% overnight, but that's not really a relevant scenario to your average company operating a shopping mall or a steel mill.
With respect to changing workloads, I wasn't thinking so much about scale, which I think isn't that hard to plan for, but more about changing requirements. If you add, remove, or change a piece of your stack the cloud gives a lot of flexibility. Add memcached, no problem, spin up some high mem instances. Need more IO on the database server, switch to an instance with fast SSDs, or a bigger instance. I think those kinds of changes are common and hard to plan for. Until it happens you probably don't know if you are disk, network, memory, or CPU bound.
Once your stack is sufficiently mature and not changing much the workload gets a lot more predictable. The cloud is really good for starting out. The danger is it's also really good at locking you in, then you are stuck with it.
True, though all the physical hardware stuff is pretty straight forward, to the point that anybody competent could figure it out in real time just by looking at the pictures in the manual. Configuring a hypervisor is the main thing you actually have to learn, and that's a fundamentally similar skillset to systems administration for the guests. Or for that matter the cloud vendor's provisioning interface. It's just different tooling.
> If you add, remove, or change a piece of your stack the cloud gives a lot of flexibility. Add memcached, no problem, spin up some high mem instances. Need more IO on the database server, switch to an instance with fast SSDs, or a bigger instance. I think those kinds of changes are common and hard to plan for. Until it happens you probably don't know if you are disk, network, memory, or CPU bound.
I see what you're saying.
My point would be that the hardware cost is now so low that it doesn't really matter. You may not be able to predict whether 8 cores will be enough, but the Epyc 7452 at $2025 has 32. 256GB more server memory is below $1000. Enterprise SSDs are below $200/TB. 10Gbps network ports are below $100/port.
If you don't know what you need you could spec the thing to be able to handle anything you might reasonably want to throw at it and still not be spending all that much money, even ignoring the possibility of upgrading the hardware as needed.
> Once your stack is sufficiently mature and not changing much the workload gets a lot more predictable. The cloud is really good for starting out. The danger is it's also really good at locking you in, then you are stuck with it.
Right. And the cloud advantage when you're starting out is directly proportional to the cost of the hardware you might need to buy in the alternative at a time when you're not sure you'll actually need it. But as the cost per unit performance of the hardware comes down, that advantage is evaporating.
But you make some good points. In general I agree it's cheaper to vastly over provision than to use the cloud. And you can do things like build an insane IO system for your database, which you can only sort of do in the cloud.
Of course this is an advantage for hosting internal company stuff, for web facing things you may need to place hardware in remote datacenters, and then you do need people on location on call who can service it. You have to generally have much larger scale for that to make sense. Even Netflix, because of the variability of their load still use a combination of cloud and their own hardware.
I didn't mean to suggest there isn't a skillset there. And that's really important when you're doing it at scale. The person who knows what they're doing can do it in a fifth of the time -- they don't have to consult the manual because they already know the answer, they don't have to spend time exchanging an incompatible part for the right one.
But when you're talking about an amount of work that would take the expert three hours a year, having it take the novice fifteen hours a year is not such a big deal.
> Of course this is an advantage for hosting internal company stuff, for web facing things you may need to place hardware in remote datacenters, and then you do need people on location on call who can service it. You have to generally have much larger scale for that to make sense.
On the other hand you have to have rather larger scale to even need a remote datacenter. A local business that measures its web traffic in seconds per hit rather than hits per second hardly needs to be colocated at a peering exchange.
It's really when you get to larger scales that shared hosting starts to get interesting again. Because on the one hand you can use your scale to negotiate better rates, and on the other hand your expenses start to get large enough that a few percent efficiency gain from being able to sell the idle capacity to someone else starts to look like real money again.
So, basically a mainframe on a chip?
Honestly, how would that work? Is all that memory coherent? There are a couple of reasons why mainframes cost so much, and some of them are technical.
I keep expecting servers to evolve into a multi-CPU non-coherent RAM, but the industry keeps doubling down on coherent RAM¹. At some point servers will turn into a single-board blade hack (that you can mount on a blade hack, piled on a hack), I wonder for how long CPU designers can sustain our current architecture.
1 - Turns out people working full time on the problem have more insight on it than me, go figure.
Intel unveiled their infamous "Tick-Tock Model" around 2007 [1]. It went according to plan for all of four years, and then it COMPLETELY fell apart. If anything, I'm willing to bet they KNEW they could hit the first few iterations. I'm guessing for hardware, you've probably got a really good idea if you're going to be able to even manufacture something in two years, let alone mass-distribute, produce, and sell it at the price point you want. I'm also pretty certain they KNEW they wouldn't hit the rest of the roadmap.
Honestly, I think it was purposefully misleading investors. I heard from dozens of engineers at the company around 2008 that there was NO WAY they would have 10nm chips around 2012 -- what the roadmap was more or less promising. And surprise, we didn't get them until 2018. Now they're promising 1.5nm in a similar time frame. I'm skeptical.
Or to put it another way, nobody is going to charge you with a crime for staying with the herd. That's a passive choice.
But when there's a dissenting voice, suddenly you have to make an active decision to ignore them. And that's when the lawsuits start producing emails about who knew what when.
End result: People intentionally (if they know better) or unintentionally (if people smarter than them are all saying the same thing) agree with the party line, even in the face of demonstrable facts otherwise.
Where did they promise 10nm in 2012? This presentation from 2011 shows 10nm in 2017: https://www.nextbigfuture.com/2011/06/intel-roadmap-from-jun... and in 2011 tick-tock was still going strong.
I think you messed up your math. Tick/tock was a process shrink every 2-3 years. Using the more aggressive 2 year cadence:
45 nm – 2007
32 nm – 2009
22 nm – 2011
14 nm – 2013
10 nm – 2015
45 nm – 2007
32 nm – 2010
22 nm – 2013
14 nm – 2016
10 nm – 2019
65 nm – 2005
45 nm – 2007
32 nm – 2010
22 nm – 2012
14 nm – 2014
10 nm – 2018/2019They pretty much nailed tick/tock flawlessly up until 10nm, 10 years out from when tick/tock was first announced. Expecting perfect 10 year predictions is some insane expectations for any company/person. There's no way in hell tick/tock's 2007 unveil could possibly be considered "misleading investors."
Intel 14nm's beginnings were far from flawless, even if it's nowhere near Intel 10nm's issues.
Your link shows 7nm in 2017, 10nm was for 2015.
>Tick/tock was a process shrink every 2-3 years. Using the more aggressive 2 year cadence:
You are confusing "Tick Tock" with "Process, Architecture, Optimization". Tick Tock is strictly 2 years cadence.
So yes 10nm missed by a large margin.
> 10 nm – 2018/2019
Intel has been making 10nm chip irrespective of yield, the current batch were months of stock piling chip before the rush to roll out in Xmas. In reality they barely got it out of the gate in 2019. And if you count Cannon-Lake as 2018, you might as well count TSMC 5nm in 2019.
>There's no way in hell tick/tock's 2007 unveil could possibly be considered "misleading investors."
There were not misleading in 2007, the executed their plan flawlessly, Intel had decent people back then. Pat Gelsinger left in 2009. It was still doing great up to 2012, Otellini retired, BK became CEO in 2013, still promising Tick Tock. That is the point where misleading investor began.
And I forgot to mention during All investor meetings Intel continue to reiterate 10nm is on track all the way until BK was gone. If that is not "misleading investors" I am not sure what is.
65 nm – 2005
45 nm – 2007
32 nm – 2010
22 nm – 2012
14 nm – 2014On the server side, big hyperscale datacenter customers have large, narrow purchase patterns. They are upending the market — ask around and figure out how many HPE or Dell CEs are still around servicing servers these days.
On the client side, similar patterns exist at a smaller scale. At the higher end Apple probably does 90% of their Intel business with like 10 SKUs. At the lower end, there’s a huge demand for cheap, and many companies skipped refresh cycles.
This was impactful imo as the old ways of dealing with manufacturing issues (sell underclocked parts, etc) are harder when Amazon has prepaid for 30 million units of SKU x.
The advances needed to achieve something like this are more in the realm of cleanroom advances than processor architecture.
We need something new, not the same old “add more cameras to the phone” kind of innovations.
It’s the engineers that will make those discoveries—the investors can shove it. All they do is freeload on innovation and cramp peoples style.
The vendor that makes the device definitely cares though I wonder how much Intel cares about consumer oroducts as percentage of mkt share compared to servers.
We can probably still increase the frequencies a bit but we definitely seem pretty close to some fundamental limit in our current understanding of physics. The frequency doublings every other year we experienced until the early 2000's are long gone I'm afraid, and they might never come back until we manage to make a breakthrough discovery in fundamental physics.
Smaller transistors reduce the I, but R goes up with smaller interconnects. The RC time constant also adds delay, probably more so than length.
That being said, 3D stacking won’t help with heat, and dielets won’t help with delay. I rather have 4 cores at 10 GHz than 64 cores at 3 GHz.
The slide seems to have been first disclosed by ASML, which has a vested interest in selling new generations of manufacturing tools.
ASML's P/E ratio is 48.02.
This won’t end well.
What vanity stock price exactly? You could hardly have picked a worse example in this bubbly market.
Fun fact: The first tank (turreted, not land-whale) was based on a tractor design.
Examples:
- https://en.wikipedia.org/wiki/Mark_IV_tank - https://en.wikipedia.org/wiki/Mark_V_tank
[1] https://wccftech.com/intel-processor-roadmap-leaked-10nm-can...
I'd expect AMD to have learned the lesson and get away with their lead this time.
*It is actually closer to 30 years.
[1] https://www.anandtech.com/show/15016/tsmc-5nm-on-track-for-q...
[2] https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-w...
[1] https://www.anandtech.com/show/13714/intel-adds-b365-chipset...
I'm being optimistic with this guesswork. Intel's historical naming is that cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm.
Well, only 10 years left to advance with silicon wafers; once improvement truly becomes impossible there presumably we'll see even more resources go into trying to find practical replacements.
> It’s worth also pointing out, based on the title of this slide, that Intel still believes in Moore’s Law.
> Just don’t ask how much it’ll cost.
I once got an opportunity to ask something similar to an Apple executive during a presentation on their hardware capabilities (it was a university event).
He laughed and answered another part of my question.
> "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000."
There's also the 1975 speech where he revised it down from a yearly doubling to once every two years.
Everyone believes 5-7nm is the cost wall for just about everyone but Apple or Intel. Some companies are actually going the opposite direction or re-spinning new chips on older processes because of cost.
What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such.
Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days.
From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance.
So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.
The first part covers EUV, which is key to advanced nodes. Then it moves on to more futuristic and tentative techniques. But the EUV part is a nice introduction for non specialist, with pointers to dig if one is interested.
It quickly introduces the various hacks we do in order to get ~30nm features on silicon. But the talk is quite dated (early 2010's), but never ceases to amaze me. Semiconductors are indistinguishable from magic indeed.
I would love to see an update with newer technology.
Highly recommended!
However, Intel is closer to 22nm than 7nm let alone anything smaller than that. ( I'm talking about consistent product lines that anyone can buy at a store ), not some Houdini show.
On the commercial side they have a huge footing and large tentacles so they don't need to worry too much about time-frames, let's hope they also don't worry too little..
EDIT: for something to read https://en.wikipedia.org/wiki/10_nanometer
I guess it's the same as LEDs.. watts/lumen.
They're not lying, it's commercial real estate.
Transistor density in millions of transistors per square millimeter is more relevant. For example: Intel 10nm is 101 MTr/mm², TSMC 7nm Mobile is 97 MTr/mm² so they are very similar.
* TSMC’s 5nm EUV is 171.3 MTr/mm²
Source: https://www.techcenturion.com/7nm-10nm-14nm-fabrication
I also would like to find any historical data on MTr/mm² just to see if there high correlation with nm names.
When comparing across generations, you'll get the most accurate picture if you stick with the same kind of chip (eg. desktop-class GPUs) and same vendor so that they're more likely to count transistors the same way from one year to the next.
Transistor count plateaued. Moore's law died.
To avoid upseting and confusing consumers with this new reality, chip makers agreed to stop delineating their chips by the size of their components, and to instead group them in to generations by the time that they where made.
Helpfully, in another move to avoid confusion, the chip makers devised a new naming convention, where each new generation uses "nm" naming as if Moore's law continued. Say for example in 2004 you had chips with a 34nm NAND, and your next gen chips in 2006 are 32nm, then all you do is calculate what the smallest nm would have been if chip density doubled, and you use that size for marketing this generation. So you advertise 17nm instead of 32nm.
Using this new naming scheme also makes it super easy to get to 1.4nm and beyond. In fact, because it's decoupled from anything physical, you can even get to sub-plank scale, which would be impossible on the old scheme.
Edit: Some comments mention that transistor count and performance are still increasing. While that is technically true, I did the sums, the Intel P4 3.4Ghz came out 2004, if Moore's law continued, we would have 3482Ghz or 3.48 TERAHERTZ by now.
That must mean, that this marketing works to some degree. Therefore, it cannot be common knowledge amongst everyone who buys PC parts. Or it might be somewhat known but still affecting their shopping choices. If it was truly common knowledge, there would be no incentive to keep naming them this way?
There is much, much worse marketing out there to tackle first.
This isn't marketing fraud because you aren't being sold transisters like you buy lumber at Home Depot.
Instead, you buy working chips with certain properties whose process has a name "10 nm" or "7 nm". Intel et. al. have rationalizations for why certain process nodes are named in certain ways; that's enough.
Funny you say that, because "two by fours" used to be 2" x 4”, but became progressively thinner as manufacturing processes improved.
That said I'm not sure why they don't sell it by it's actual size.
"Recent technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading foundries call their nodes"
..."At the 45 nm process, Intel reached a gate length of 25 nm on a traditional planar transistor. At that node the gate length scaling effectively stalled; any further scaling to the gate length would produce less desirable results. Following the 32 nm process node, while other aspects of the transistor shrunk, the gate length was actually increased"
"With the introduction of FinFET by Intel in their 22 nm process, the transistor density continued to increase all while the gate length remained more or less a constant."
I'll repeat it for you see you seem to keep missing it: transistor density continued to increase
> Transistor count plateaued.
No. Transistor count has continued to increase. The "nm" numbers still correlate with overall transistor density. The change is that transistor density is no longer a function purely of the narrowest line width that the lithography can produce. Transistors have been changing shape and aren't just optical shrinks of the previous node.
[1]https://en.wikipedia.org/wiki/Dennard_scaling
[2] Though Dennard's paper came out in 1974 and the term "Moore's Law" was coined in 1975 so they've always been a bit confused.
"Anyone seen the new V12s this year?"
1) Transistor density has continued to increase. The original naming convention was created when we just used planar transistors. That is not the case anymore. More modern processes create tertiary structures of "nodes" which condense the footprint of packs of transistors. Moore's law didn't die. It just slowed.
2) Clock speed is not correlated to transistor size. The fundamentals of physics block increases in clock speed. Light can only travel ~11cm in 1 billionth of a second (1GHz). Electricity can only ever move at 50%-99% the speed of light dependent on the conductor. What's the point of having a 1THz clock when you will just be wasting most of those clock cycles propagating signals across the chip or waiting on data moving to/from memory. Increasing clock speed increases cost of use because it requires more power so at some point a trade-off decision must be made.
[1]: https://en.wikipedia.org/wiki/Moore%27s_law#/media/File:Moor...
Comparing raw CPU speed seems like a bad metric. A new i5 clocked at 3.1Ghz will absolutely wipe the floor with a 3.4Ghz Pentium, even for single threaded workloads
https://cpu.userbenchmark.com/Compare/Intel-Pentium-4-340GHz...
Due to the fact that making a 7nm gate width is not only impractical (even the most advanced EUV lithography can't do it) but also would make the transistors work terribly--the fact that everyone form 2005 was referring to--the industry was forced to innovate. Their clever solution was to change their naming convention, and instead of naming each technology node after the actual gate width they just assign them a arbitrary number which follows moores law. [1]
The actual gate width for a '7nm' process is somewhat ill defined (they look nothing like a textbook transistor), but depending on how you measure it the number comes in somewhere between 30-60nm. [2] Note that there is a number in the 7nm dimensional chart that comes in at 6nm, but that is the gate oxide thickness, and is actually getting _thicker_ over time. For example back in 90nm it was 1-2nm thick.
That said, those skeptical of us ever producing a '7nm' transistor back in 2005 were right--by the naming convention used in 2005 we are still at ~40nm. I am sure that you will be able to buy a '2nm' processor according to the roadmap, but the actual transistors are still going to have a gate width closer to 30nm and their electrical performance is going to be within a factor of 2 of our current '7nm', and honestly probably going to be clocked slower.
A 45nm process:
i7-880, 45nm
774 million transistors
296 mm2
i7-6700k, 14nm
1.75 billion transistors
122 mm²
The expected scaling is that transistor density should have scaled with gate length squared (since the structures are laid out in a 2-D grid, for example the 0.8um process used in the 8088 had a sram density of 120um^2, compared to 1um^2 squared for 90nm, a factor of 120x for a roughly 10 times smaller process), so one would have expected a 165x improvement moving from 90nm to 7nm.
Unsurprisingly, the missing factor of 5 is the same factor between the process node name ('7nm') and actual gate length (~35nm).
Every semiconductor has a lower limit, for silicon it's ~10nm.
If.you are visual, Coventor has some nice visualizations. And I really like the work from Nikonov and Young.
If you really.want to get into the ideas, the series.of.papers and notes on E-tau scaling rules are great. Maybe not complete, but good.
Ideas for density aren't too hard: shrink pitch and fold into the z dimension. 3DNand is a folded NAND string, after all.
On materials, it really is driven by etch and lithography (collectively, patterning). Mostly not materials themselves.
"If EUV doesn't make a more performant chip, what it does?" EUV is there to alleviate extreme process costs associated with multiple patterning, and process cycle time.
Even if EUV tool does 1 exposure a little bit slower than quadruple patterning, it can do 4 patterning steps in one — a very huge thing in process technology.
You have then lessen the amount of thermal processes performed on the device. You may have more defects, but on overall higher quality, higher performance devices in the end.
Would that also remove some patterning constraints? Give the pattern "more freedom".
Not to say it could never happen, but given how many years Intel has spent on 10nm with it always been 'next year' tech year after year, 7nm in 2021 seems overly optimistic for me.
I guess time will tell if they got it right this time.
In fact GlobalFoundries also failed their 7LP (7nm). As a result they stopped pathfinding and research for 5 nm and 3 nm and quit the race. They are moving to more specialized chips.
Fab cost for new process has grown each year for decades. Now it's something like $20 billion. Stakes grow at same time as things get more hairy and complicated 'down there'.
Less power consumption also means less heat generated. I think heat dissipation is the main roadblock to faster CPUs (faster in terms of clock speed).
IANAEE but I think the speed of light becomes a big issue at higher clock speeds. Putting transistors physically closer to each other helps reduce problems with propagation delay.
That said, transistors actually stopped shrinking a while ago. They are getting packaged nearer to each other, they have changed from horizontal to vertical, and they are changing the width/length ratio, but they are not really shrinking.
Edit: oof with the down votes. Jesus people; comma added for clarity.
Because the only energy added to the planet comes from the sun and the only viable option to collect that energy are trees and plants.
(I'm going to post this comment on every naive technology optimist post, you can downvote me all you want, I have to do this to be able to sleep at night, fake karma is not more valuable than real karma)
Actual nanotech will allow for gates that are legitimately just a few nanometers across.
You're essentially trying to replicate what cells do in a growing embryo, and even with several billion years of evolution that is still a very very error-prone process.