Jim Keller, the designer of "Zen" architecture, is now working for Intel... https://web.archive.org/web/20180426124248/https://www.kitgu...
Incredibly accomplished man, I don't think he's going to stay in one place for very long. He'll probably come back to AMD at some point or another.
What RISC-V needs at this point is marketing and a company with a dedicated sales team, not technical competency.
If RISC-V wins, it will be because it has a better developer/enthusiast/hacker story, but if so it will take a longer time to get there.
Either way, I hope for he sake of our infrastructure that an open standard wins out, and that we have enough competing manufacturers that we never have a repeat of Intel's utter dominance.
Most of the hype for RISC-V seems to be in tiny embedded stuff (e.g. WD's disk controllers) and academia (naturally). SiFive has finally made an out-of-order core, but I don't really see the market for big unix-capable RISC-V. RISC-V is really a royalty-free "MIPS in a trenchcoat", so expect it to be used where MIPS is used now.
ARM is everywhere, from smartphones (unfortunately Qualcomm dominance, but Apple is kicking ass in performance) to AWS EC2 (in-house silicon!) to massive HPC clusters (Fujitsu A64FX is impressive, they use HBM2 RAM (!) to make a SIMD-capable CPU into something almost GPU-like in a way). AWS has basically ensured that ARM is the next ISA for servers :P
> AWS has basically ensured that ARM is the next ISA for servers :P
These hyper-scalers (inc. Microsoft, Google, Alibaba...) will take a little bit of everything, because they generally can always find cookie-cutter workloads impeccably suited to any architecture, but also as industrial diversification, for R&D, etc. Like AMD, the presence of some ARM CPUs in the biggest datacenters says little about market forces, what matters is how many actual FLOPS are effectively handled by each vendor. I'm positive Intel still has the lion share, and the inflexion point in favor of AMD (nearest competitor) would be 2023 at best, more likely 2025-26 assuming Intel eventually catches up in price/perf/W.
A reasonably heterogenous infrastructure is very good when you're an order of magnitude bigger than entire datacenters, or so I hear.
I share your concern that RISC-V is currently largely confined to the MIPS space; and indeed it's a totally different ballgame to break into ARM's space, let alone x86 (but I don't see why RISC-V would seek the latter, especially considering POWER is up there).
[1] https://www.phoronix.com/scan.php?page=news_item&px=Libre-RI...
My point was more that economies of scale happen with killer products (e.g. how CISC won over RISC back in the 90's, it wasn't about tech but about product, and as you say it falls down to sales and marketing). Somehow a guy like Jim got involved in some of the best scalers out there (AMD's x64, Apple's A chips, Tesla's self-driving AI, AMD's Zen, now something at Intel with 3D stacking most likely, and next...?)
Here's to RISC-V, anyhow!
I just hope the people involved in RISC-V are collectively able, as an industry, to deliver the kind of fabrication process backbone funded by great products 'agressively' marketed that saw the victory of pretty much all standards — CPU instruction sets very much included. A combination of very applied engineering + shrewd business mindset.
I assume that RISC-V still has a gap (relative to ARM) between the ISA/HDL levels and getting to an actual tape-out. But I think SiFive et. al. can tackle it.
* ARM wasn't directly in the manufacturing business. This meant they weren't a supply chokepoint when demand scaled by a factor of thousands. Just take the IP core and fab it yourself!
* They triangulated the market unexpectedly well.
There was a definite gap in the market between "performance at any cost" big architectures (x86/Itanium/Power/PA-RISC/SPARC) and "Draws no current, but gets winded running the clock for a VCR" (6502/Z80/68HC11/Atmel/PIC) little ones. For a long time, this was filled by on an ad-hoc basis-- one-off designs for game consoles, set-top boxes, and ahead-of-their-time smart appliances. Most of these were closed, single-vendor, no-interoperability systems where "ease of integration" and "off the shelf tools" didn't really matter, so we had all sorts of bit players.
It took the arrival of full-power handheld devices with third-party software support (PDAs and then smartphones) for a large demand to appear, and ARM was ready with a product line that fit the space well.
Compare the alternative, a world where we had had x86-based Windows CE devices and eventually iPhones. Intel/AMD/VIA would have been scrambling to put together the diversity of custom designs these devices cried out for. It would have required a massive respin of their architectures (look how hard it was to get Atom into a phone-ready state, and even then it did poorly) and then backlogged their foundries.
Look at the SiFive team for starters. Anyway, here's to RISC-V!
He can't be a genius of THAT magnitude, that would be a miracle.
I go to company to company consultanting, and the companies almost always have very competent staff they just don't listen to.
Semiconductor engineering was hurt badly when it tried to borrow work culture from the dotcom world, and treating engineers as disposables.
I myself know of other man of equal magnitude in the analog world. He worked in electronics for 24 years, most of it in China. He worked for one of my employer, where he was deservingly fired for failing a potentially multi-million buck project. Apple hired him, literally, next week. I have suspicion he had his hands on Apple's Air Pods.
It was tough to work with him, he has a reputation of "Shenzhen's Rob Widlar." Very few companies can make a working environment for him.
Maybe it's just once the corporate gears of a company have aligned to invest in something new/interesting - he's interested and they're paying.
Though the first step for you would be to work on projects you're more passionate about, and that are more technically challenging. A billing site (judging by your HN about section) won't challenge you in a way that will make you get better.
He's the Kelly Johnson of silicon.
What term do you think they'd use, and why?
If you ask a Sun employee: "Enemy #1."
Less sarcastically: "slightly above average."
x86_64 is a nightmare, and we're a decade behind where we could be because it was what the industry settled for.
Unfortunately, I think a much more likely situation is that x86 (/64) is only slightly hobbling things, and Intel are easily able to push past that with technical craftiness. As in many other cases, implementation trumps theoretical design.
A new architecture can offer that much advantage; x86_64 wasn't even the third most-performant implemented ISA when it was released, and every other ISA makes gains far faster than it. SPARC and POWER are still competitive with it despite having 1/1,000,000th the amount invested in them, and in just a few years and with comparatively nothing invested into it, RISC-V is starting to rival a portion of the chips (though not the upper line of them yet).
It "won" because of backwards compatibility, nothing more.
The evidence is that architectures are just not as important as all that. x86 is clearly pretty bad in many ways, but clever tricks and microcoding have been able to overcome those issues.
This is a complete misinterpretation of the above comment.
The issue was chipsets and peripherals, not POWER performance (which generally always beat x86 at the same point).
The problem was that the entire ecosystem was built around communicating with an x86. So, you couldn't get a Northbridge or Southbridge equivalent that was even remotely close in performance or power consumption to those in x86 space.
Unless you decided that you were going to take on everything in chip design, you couldn't compete. And Apple didn't decide to take on everything until Intel told Apple to pound sand and pissed Jobs off.
The 601 based PowerPC's were the first to be able to do 3D graphics on the microprocessor well.
The G4 based titanium Powerbooks were sufficiently better that they became iconic at a time that Apple wasn't regarded that well.
Sure, the G5 and up were disastrous, but the writing was on the wall well before that. Chipsets on the G3 and G4-based systems used more power than the processor and that only became untrue because the G5 was quite so poor.
Do you have a source for this? First time I've seen anyone claim that the G5 was competitive with contemporary Intel CPUs.
Those were different times for Apple. The ship was noticeably turned, but the storm not over yet.
X86_64 is genius because it is the perfect example of the art of the possible.
It drove SPARC into irrelevance, forced Intel to adopt it instead of Itanium and drove PowerPC out of consumer computers. I'd love to have a nightmare like that on my resume.
https://news.ycombinator.com/item?id=276418
There's plenty of criticism of CISC in general, but that gets into flamewar status.
A lot of modern abstraction, vulnerabilities and inefficiency can be summed up with "x86_64 sucks to write for, so let's build a new (or recreate an old) abstract machine!"
In its quest to maintain fifty years of (near) compatibility with an architecture originally used in a calculator, the industry created a monster.
There's a reason Apple (and Sun and MIPS before it) was able to get competitive with Intel's chips despite only getting a silicon team like half a decade ago and using an architecture generally seen as low-performance: they ruthlessly removed cruft, cutting ties with backwards compatibility in the process.
Backwards compatibility is a scourge unto innovation and ease of use, as even Intel saw (IA64, for all of its faults, was better than x86_64 in virtually every way).
I have a lot more criticism of x86_64, and can get a lot more technical in that criticism, but this comment is already getting a bit on the heavy side.
Modern superscalar OoO is pretty much like that, except there is a piece of hardware internally that does it, almost like a hardware jitter. This freedom both means the magical compiler doesn’t have to exist but also it allows processors to have varying amount of execution units. See that you could actually use one more int alu? Just add it and even older software is able to automatically get the benefit.
in summary: x86 is ugly (and below is why I think so) but we don't care because compilers enable us to just forget about what ISA we're using. This is a good thing. This is the way it should be. But it's also an example of what the OP was talking about -- bad hardware design (in this case the x86 ISA; the actual hardware is quite good) not mattering because software is sufficiently good
While the core is great, I think the biggest contributors to the success are a few decisions outside of the design of the Zen core.
One is an investment back in the Opteron days for an efficient, scalable, low power, low latency, high performance serial interconnect. This is a key enabler for the new chiplet strategy that has paid off so handsomely for AMD. Now a single piece of silicon can scale from low end Ryzen through the highest end servers without having to divide their limited R&D budget across numerous different designs.
Additionally selling off global foundries enables them to pick the best fab per generation, something that Intel can't, or at least hasn't done.
So Intel had a set back on the fab where the difficulty (chip yield) is increased by their larger chips. While AMD can switch fabs (they switched from global foundries to TMSC at 7nm) and make much smaller chips. The top of the line Epyc chip has 9 chips inside (I/O + 8 CPU chiplets).
This positions AMD Particularly well for the future, they could now rev the I/O chip for DDR5, more memory channels, or any other performance tweak without having to re-engineer the CPU chiplets.
It also doesn't require all the chip related technologies to move in sync. The I/O chiplet is actually made on an older process than the CPU chiplets. If the PCI-e 4 I/O chip was late, AMD could have shipped a PCI-e 3 I/O chiplet. If mid cycle PCI-e 5 becomes a must have AMD would have much less engineering to fix it.
The Infinity Fabric (current generation that evolved from hypertransport) is a cache coherent serial network that can also do PCI-e (non-cache coherently). This can be swapped on a per serial connection basis as needed.
Seems like they could rev the PCI-e side without changing the IF side. The I/O chip has separate connections for off chip, so they could use PCI-5 there and not change the connections to any of the CPU chipets.
At least it seems that way... corrections?
Mike Clark is the person who designed Ryzen . He is the guy who came up with the name Zen as well.
https://www.statesman.com/business/20160904/amid-challenges-...
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He creates the "oh shit" moment at company A regarding company B, then goes and works at company B, to create an "Oh shit" moment for company A.
Jim's brother-in-law is Jordan Peterson. Yup, that Jordan Peterson. Small worldish thing I guess?
(Now these 2 posts look like s tabloid, speaking about perdonal lives)
Is it because of not truly knowing what it takes to do VLSI nowadays or just hoping that if one man did it, it can be done again?
To be fair many people that are the single reason for success of a company do not claim it themselves.