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Comment by jonsen | Hacker News Reader

In a way everything is microcoded. The 6502 was hardly microcoded in the general meaning of microcode:

“An alternate approach, used in many microprocessors, is to use PLAs or ROMs (instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. The MOS Technology 6502 is an example of a microprocessor using a PLA for instruction decode and sequencing.”:

https://en.m.wikipedia.org/wiki/Microcode

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Having written microcode, and with the gate level information we have on the 6502 now, I can totally tell you that it's microcode. Some people get confused for some reason if they've only been exposed to vertical microcode.

If a 6(?)-state PLA counts as microcode, what CPU isn't microcoded?

Probably unpipelined RISC designs with exclusively single-cycle instructions. The instruction decoder just consists of setting a bunch of multiplexers to the right states for that instruction.

The distinction might be whether the instruction breaks up into a sequence of discrete internal operations. Implementing this as a hardwired state machine is an optimization.

21 states, the instruction register is part of the state selection.

And classic 5 stage RISCs like most MIPS don't typically have microcode.

Looking at what the PLA actually does, though, isn't it tantamount to a cleverly compressed microcode ROM? As far as I understand it, the opcode and cycle number select a "word" of control signals to spit out, and the PLA aspect is primarily used to allow multiple permutations of cycle+instruction to select the same "microinstruction" without duplicating it as a conventional ROM would require.

edit: I realize that in some trivial sense any combinational logic is tantamount to a compressed ROM, but I mean that even in a design sense this seems like it's not far off from a deduped array of microinstructions.

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