CPU of the Day: Motorola MC68040VL | Hacker News Reader

CPU of the Day: Motorola MC68040VL

cpushack.com

87 pointsprotomyth23 comments

The time period is very interesting to me. The 680x0 story is pretty well documented, but their 88k chips + MVME [1] were also popular in specialized devices like firewalls. There was a time when Motorola was kicking Intel's butt in specialized areas.

[1] https://en.wikipedia.org/wiki/Motorola_88000

Motorola was even kicking ass in PCs, although you had to be selective with benchmarks to show an advantage over Intel Pentiums.

When Steve Jobs came back to Apple, he sanctioned a marketing campaign emphasizing the performance of the Motorola PowerPC G3, with Intel chips pictured on the back of snails.

One of the ads: https://www.youtube.com/watch?v=jqMruSb_SuE :)

Lets not forget "the world's fastest personal computer" https://www.businessinsider.com/the-20-most-sexy-violent-and...

'The ASA has banned two separate Apple commercials from airing in the UK. In 2004 the Power Mac G5 made unsubstantiated claims of being "the world's fastest personal computer" and in 2008, an iPhone commercial was banned for saying that it could access "all of the internet" even though it couldn't support Flash.'

>in 2008, an iPhone commercial was banned for saying that it could access "all of the internet" even though it couldn't support Flash.'

So, not even "all of the web", never mind "all of the Internet", which Apple still doesn't support.

There's an over $5000 bounty for someone to rewrite the GCC backend for the 68k/ColdFire so it can be kept and maintained going forward for newer versions.

https://www.bountysource.com/issues/80706251-m68k-convert-th...

> [microcoding] is common in processors today and allows greater flexibility

Microprogramming was already widespread since the 1960s. The early microprocessors, such as MOS Technology’s 6502, too, used microcode (in its “hardwired” form).

In a way everything is microcoded. The 6502 was hardly microcoded in the general meaning of microcode:

“An alternate approach, used in many microprocessors, is to use PLAs or ROMs (instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. The MOS Technology 6502 is an example of a microprocessor using a PLA for instruction decode and sequencing.”:

https://en.m.wikipedia.org/wiki/Microcode

Having written microcode, and with the gate level information we have on the 6502 now, I can totally tell you that it's microcode. Some people get confused for some reason if they've only been exposed to vertical microcode.

If a 6(?)-state PLA counts as microcode, what CPU isn't microcoded?

Probably unpipelined RISC designs with exclusively single-cycle instructions. The instruction decoder just consists of setting a bunch of multiplexers to the right states for that instruction.

The distinction might be whether the instruction breaks up into a sequence of discrete internal operations. Implementing this as a hardwired state machine is an optimization.

21 states, the instruction register is part of the state selection.

And classic 5 stage RISCs like most MIPS don't typically have microcode.

Looking at what the PLA actually does, though, isn't it tantamount to a cleverly compressed microcode ROM? As far as I understand it, the opcode and cycle number select a "word" of control signals to spit out, and the PLA aspect is primarily used to allow multiple permutations of cycle+instruction to select the same "microinstruction" without duplicating it as a conventional ROM would require.

edit: I realize that in some trivial sense any combinational logic is tantamount to a compressed ROM, but I mean that even in a design sense this seems like it's not far off from a deduped array of microinstructions.

In college in the late 90s, I remember an assignment to optimize the microcode for an instruction in a hypothetical computer. I had a lot of fun doing that and came up with a much shorter solution than my professor thought possible.

I never ended up doing any low-level programming professionally though. The person I worked with that was the best at SQL, I heard hated his college course with FPGAs.

Here's an MCF5102 based system, the Alpha Micro Eagle 450. Alpha Micro used the MCF5102 in their ColdFire-based systems for its '040 backwards compatibility.

http://ampm.floodgap.com/www/e450.htm

Big fan of your work.

Once I get my desk rebuilt I will fire up my PowerPC collection again.

”It has dual MMUs”

What are dual MMUs good for? One for kernel code and one for user-mode code? (Does that mean less cache flushing during context switches?)

Guessing it's neat for I/O?

I wonder if this is what we would call split TLB today: one for instructions and one for data.

This is correct. It had one MMU for instructions and one for data.

The two MMUs use the same page table. There is only one page table root pointer (actually two: one for user mode and one for kernel mode). But there are two translation caches for code and data (usually called TLB; called ATC in the 68040).

However, there are separate configuration registers for code and data address space that can be used to define which parts of the virtual address space should be translated and which parts are directly mapped to physical addresses without translation. Therefore, strictly spoken, the instruction address space is not necessarily identical to the data address space, despite having only one page table.

By the way, the possible difference between instruction and data address space can have interesting effects.

Amiga programmers, do you remember the (bad) habit of putting data fields directly into the code? Like this fragment:

    ...
    jsr OpenLibrary(a6)
    move.l d0, gfxbase
    rts
    gfxbase dc.l 0

Imagine now what could happen in the above move.l instruction if the address "gfxbase" is translated differently from the addresses of the instructions :)

Ooh good times :)

Reply on news.ycombinator.com