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Comment by fulafel | Hacker News Reader

"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.

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God I hate that term. It's not your secret sauce intellectual property, it's a fucking library.

Possibly the biggest reason FPGA/ASIC tech has lagged so hard behind CPU/GPGPU in terms of consumer use is because they have managed to use their hardware to completely stifle all open source software (they even go to some lengths to distance themselves from the term "software"). FPGA libraries are almost always encrypted and have to be treated as a true black box when designing. Doing things as mundane as interacting with a PCIe bus or simple signal filtering are all locked away behind ludicrously overpriced "IP" packages that are often vendor specific.

Interacting with a PCIe bus does not seem "mundane" to me. Analog electronics is hard, and, just as importantly, process-specific (and the details of any one process are generally kept strictly confidential to the fab, with tightly-binding NDAs). Now, when it comes to pure digital logic I agree, but that's also where open hardware (with meaningful contributions by SiFive themselves) has been most successful.

The analog parts of PCIe interfaces are not programmable. The artificially black boxes we are talking about are purely digital. They use fixed resources but we are not asking for the design of those parts.

Hell, I'm glad Symbiflow[0] exists. Once the toolchain is a little more mature, a library of modules with OSHW licenses is bound to pop up, perhaps even integrated into some sort of IDE.

[0] https://symbiflow.github.io/

Why can't a library be IP?

IP means nothing. It's a poorly defined conglomerate of vastly different laws, like about brands, patents, models, etc.

A library is typically "protected" (that is: artificially restricted) by copyright, and the situation is then blurry but in some cases also patents (depending on the region of the world and/or good lawyers knowing the magic words to patent non-patentable things) and trade secrets.

I think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout.

SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).

"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.

Interestingly, although all the RTL for the SiFive Freedom platform is in the SiFive's GitHub repository, and they've produced chips and boards (with public schematics and BOM), the hard IP doesn't appear to be public.

I wonder if this is because the hard IP is specific to the fabs' trade secret tooling, and so subject to their NDAs, making it impossible to distribute publicly.

You're on point with the second paragraph. I only know of one chip fab that has it's design rules public, and they're an open source fab running out of HKUST that'll give you about Arduino level gate counts.

Why can't a fab with something like 28nm use public design rules? I guess there aren't valuable trade secrets still in a process that old. But some chips can usably be made on such a process.

There's a lot of mixed-signal specialty ASICs at the 350 nm and 180 nm nodes. As long as you don't need the density, it's a great option. Masks are relatively cheap and the processes are dialed in extremely well at this point. Just because the tech is 20-30 years old doesn't mean it's not useful.

There's absolutely valuable trade secrets even at 28nm. For starters, a fab's work at 28nm would absolutely inform descions on newer nodes. Additionally, the older nodes don't just shut down their lines, but are dependent on continued use to pay off their massive capital investment. They're still competing with the other 28nm fabs.

I wish one of them would just try and release a 180nm process in a way that allows public domain maskset distribution.

If it flops, so be it; if not, many people like myself can suddenly start hacking on analog or mixed IC designs for potentially exotic things, like analog-computer-based UAV controllers that integrate the control loop with e.g. external feedback like simple doppler/chirp radar to reach microseconds of feedback latency and thus enabling monolithic closed-loop control.

A miniaturized version of https://www.research-drone.com/en/ with the blade's counterweight being a single neodymium magnet in an outrunner configuration and a ferrite stator fabricated using SMD inductor technology to target the 5g (+ payload + battery) UAV class would be interesting, but the ~3KHz (typical disc loading and high subsonic tip speed) rotation rate (~200k rpm) make software control of the motor driver difficult.

When you are selling IP like this you would need to do your own physical design due diligence, even if the deliverable is just some Verilog code.

IP cores are sometimes deployed on FPGAs though, so that can be a working chip (depending on definitions).

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