Ive seen plenty of HDL written by people who are software engineers, it's not good. It seems to me most software engineers struggle with visualizing their behavioral code as a schematic and tend to write code that is not very synthesis friendly and overly convoluted. Not to mention most issues with hardware engineering cant be solved by a google search of how to do X in Verilog/VHDL, problems tend to be device specific which means you NEED to understand your tool chain and can't abstract away the code from from the implementation like you can with most high level software to the ASM/binary.

Software Engineers can learn HDLs in one or two weeks about as well as hardware engineers can learn C++ in one or two weeks. Will they get to something syntactically correct? Sure. That doesn't mean what they'd be able to write would be useful. And it's not just the toolchain, it's about understanding that HDL isn't a tool for programming FPGAs, it's a tool for programming hardware and FPGAs are one very specific target for which writing performant code requires a high level of knowledge about the underlying structure of the FPGA.

It's a chicken and egg problem too. Toolchain friction and depth of knowledge required is one part. Ubiquity of FPGA silicon lying around in the average programmer's (and end-user's) machine is not there.