I think that RISC-V has a long way to go to be actually competitive with ARM on a IPC basis. Although it is great to have more competition in the market I believe that this is more of a 5-10 year goal rather than distinctly near term.
Don't get me wrong, I would love a RISC-V chip that is competitive with the ARM chips in smartphones but I think we are quite aways away from it for the time being.
RISC-V is most successful as microcontrollers who do not have to be state-of-the-art fast, they just have to work reliably.
Assuming the best performing BOOM chip refers to the 2018 HotChips tapeout, that chip operated at 1.0 GHz. The lowest speed Ivy Bridge Core/Pentium (a design getting close to a decade old, FWIW) was 2.5 GHz. This means on a core-to-core basis Ivy Bridge is 2.7x more performant. This ignores the benefit of the additional core count of the Core series of Ivy Bridge procs.
Today's 9900K is also around 40% more performant than the comparable Ivy Bridge (4960X). That would suggest the performance gains modern Intel design holds over BOOM is closer to 3.8x on a core-to-core basis.
Being within an order of magnitude performance-wise is impressive given that BOOM is mainly a one-man show. That said, having about a quarter of Intel's present chips' performance doesn't strike me as particularly "close".
I appreciate and understand the discussion around IPC and how BOOM is a significant improvement on the state of the craft. I cut my early programming teeth by developing PPC and SPARC versions of my business' embedded software products. I'm a longtime fan of alternative architectures and keep up with the industry through attendance at events such as Hot Chips. I am familiar with the terminology here and am not disputing it or the findings of the benchmark.
My point was that using IPC in this way obfuscates how far these architectures have yet to go to be competitive in certain markets. Said market competitiveness was the original discussion topic up-thread.
I agree that being able to build something that runs at speed is equally important but IPC does have an exact meaning
Most of that relative performance gain is not from increased speed but from decreased speed of older processors due to meltdown (and spectre) mitigations. In the past the 4960X and it's contemporaries were much faster.
Process tech is slowing, so I think that costs of the best processes will go down and we'll see more competition for CPU designs.
https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas...
In the book the authors compare the expressiveness (and thus code density) of code implemented with the RISC-V ISA with instructions for x86, ARM and MIPS. They show that the RISC-V ISA is able to give ARM a good fight in terms of IPC, and that it beats MIPS. (Mainly due to the delay slots which can't be filled in many real world cases.)
They also show why the R5 should make implementations scale better in clock speed compared to ARM. This is the kind of stuff Patterson has been doing research on the last 3-4 decades, and it is quite interesting to see how this experience has guided the design of the RISC-V ISA.