The instruction decoders on x86 processors consume a lot of silicon. x86's instruction retirement also imposes additional overhead due to book-keeping on the scheduler. Eliminating the x87 stack-based FPU is been a gradual process involving an evolving SIMD instruction set that started as a hack.
In reality, resources trumps ISA. x86 has the advantage of hand-optimized logic combined with the best high-performance VLSI manufacturing in the industry.
In spite of that, Itanium blows the doors off of every x86 processor built on the same fabrication technology -- notice that so far, the Itanium and x86 contemporaries are built on fab processes that have been two generations apart, with the high-volume part using the newest process.
Btw, I tend to agree with you,and think Intel's engineers are just being lazy wrt power. I expect this Nvidia chip to get crushed technically when Intel's engineers gear up and really work on power (like they did when Transmeta's Crusoe came out).
Why is Intel having trouble broadening their horizons? Is it an institutional thing, that the teams not working on the main (and most profitable) CPU product lines just can't get the resources needed to catch up with the competition? Intel always has the latest and greatest fabs, but it seems like the designs they're producing for these new product lines are completely squandering that advantage and then some.
Thumb has benefits, but there are also limitations which is why I wouldn't call it a replacement.
One of the big differences is that you now need a marker instruction for predicated sequences, but obviously the encoding is quite different.
That said i've heard/read that Thumb2 tends to be the optimum size/space trade-off, but that's not because it's somehow more 'cisc'.
I don't think Intel is being lazy, but Atom is certainly an immature design and the mainstream Intel cores target a much higher level of performance; brainiac cores are fundamentally inefficient because power efficiency decreases as performance increases (in other words, each marginal increase in performance costs more in power than the previous one).