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Comment by wtallis | Hacker News Reader

Which way do you think the issue was settled? Last time I read much about the issue, there seemed to be decent arguments both ways: CISC allows denser packing of instructions, but all CPUs are RISC internally, but the CISC decoders are negligible overhead, but good compilers are easier to write for RISC, ...

How valid are the various arguments these days? The compiler complexity argument seems to work well against the Itanium, but I'm not sure that it makes much difference between ARM and x86 or x86_64. The instruction decoders on an x86 processor really do look minor on paper, but why hasn't Intel been able to produce a chip with competitive performance per watt, especially given their fab advantage? It seemed like they were really trying with the Atom, but it still hasn't gotten down to the power levels where ARM really shines, even though the high-end ARM cores are now out-of-order superscalar designs.

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The consensus is that RISC vs. CISC doesn't matter because microarchitecture trumps ISA: the cost of instruction decoding is now small, I-caches negate any difference in code density, compilers can produce efficient code for any reasonable (i.e. non-Itanium) architecture, etc. I am honestly surprised to see Dally's complaints.

Do you have any insights into why then x86 chips consume so much power than the ARM equivalents?

Btw, I tend to agree with you,and think Intel's engineers are just being lazy wrt power. I expect this Nvidia chip to get crushed technically when Intel's engineers gear up and really work on power (like they did when Transmeta's Crusoe came out).

There's probably quite a bit of truth to that, but in recent years Intel has had two dramatic under-performers (Atom can't come close to ARM and the on-chip graphics for their mid-range processors have yet to fill the gap left when Intel forced NVidia to stop making integrated graphics chipsets) and a complete failure (Larrabee) that seem like they shouldn't have happened given Intel's dominance.

Why is Intel having trouble broadening their horizons? Is it an institutional thing, that the teams not working on the main (and most profitable) CPU product lines just can't get the resources needed to catch up with the competition? Intel always has the latest and greatest fabs, but it seems like the designs they're producing for these new product lines are completely squandering that advantage and then some.

I suspect that the inability to bring down power isn't just "laziness" on Intel's part. Decreasing power consumption is (more or less) equivalent to increasing performance per watt - an area where Nvidia and ARM designs may simply be better.

Many arm chips support both a RISC ISA (the original ARM), and a more CISC-y ISA (thumb2). They consume less power and perform better with the latter. So well, in fact, that some chips don't even bother with the legacy RISC mode.

legacy RISC mode? last time I checked it was called the ARM mode, which is the absolute standard.

Thumb has benefits, but there are also limitations which is why I wouldn't call it a replacement.

Not anymore - Thumb2 is the new standard and supports everything that ARM does (at least, the last I read it did).

One of the big differences is that you now need a marker instruction for predicated sequences, but obviously the encoding is quite different.

Thumb and Thumb2 really aren't any more 'CISC'-y then ARM; about the most cisc aspect would be that thumb2 supports two different instruction lengths (2 and 4 byte) whereas ARM supports only 4 byte instructions.

That said i've heard/read that Thumb2 tends to be the optimum size/space trade-off, but that's not because it's somehow more 'cisc'.

There really aren't equivalent x86 and ARM processors yet; IIRC even the slowest Atom is faster than the fastest Cortex A8 (I'm still waiting on A9 benchmarks).

I don't think Intel is being lazy, but Atom is certainly an immature design and the mainstream Intel cores target a much higher level of performance; brainiac cores are fundamentally inefficient because power efficiency decreases as performance increases (in other words, each marginal increase in performance costs more in power than the previous one).

If this were another TransMeta, I'd agree, but the situation is quite different, because Intel is very early in their learning curve on graphics, and nVidia is quite far along in their learning curve on graphics and high-performance computing. They actually have a decent shot at competing with Intel in the low end of the desktop market by making up with the GPU what they end up lacking in the CPU.

+1 for "compilers can produce efficient code for any reasonable (i.e. non-Itanium) architecture".. laughed out loud, until i tried to explain why i was laughing to my wife. She thinks i'm a geek.

I don't think that's accurate.

The instruction decoders on x86 processors consume a lot of silicon. x86's instruction retirement also imposes additional overhead due to book-keeping on the scheduler. Eliminating the x87 stack-based FPU is been a gradual process involving an evolving SIMD instruction set that started as a hack.

In reality, resources trumps ISA. x86 has the advantage of hand-optimized logic combined with the best high-performance VLSI manufacturing in the industry.

In spite of that, Itanium blows the doors off of every x86 processor built on the same fabrication technology -- notice that so far, the Itanium and x86 contemporaries are built on fab processes that have been two generations apart, with the high-volume part using the newest process.

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