If I understand it correctly, 3 nm is less than ten atoms. Cannot this make the technology much less reliable due to quantum effects and interference?
On top of all that, the design rules become crazy at small dimensions. You can't just make a sharp bend in a wire because the high frequency component of the bend causes ringing in the interference pattern of the EUV laser.
* - I'm just a software guy with a BSEE... I'm curious what a semiconductor designer has to say about all this.
Sharp bends don't happen because they cause large fields which in turn cause dielectric breakdown. Most critical metal layers are oriented in a single direction. 2D printing with EUV isn't really an issue.
There are three components which make the area of a cell that are used to infer the scaling. The fin pitch, the metal pith, and the cell height (track count). An older technology (22nm) might have a 9track, 40nm by 60nm size. 14nm would be 9T2842, 10 would be 7.5T2638, 7 would be 6.5T2638 with SDB, and 5 might be 5.5T2230
Numbers very approximate, but the key is that design compaction (which requires major physical integration changes) coupled with reduced key pitch shrink.
The nice part is that you tend to get more design innovation, because you are no longer competing with shrink. And the relative cost of additional masks and layers is low.
IBM fabricated single-atom transistors that worked with adequate reliability back in the 1990s, IIRC. I don't know how bad the noise problem you allude to really is.
Wikipedia has a nice picture of the lattice structure:
https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Visu...
Part 3 of the picture is a 3x3x3 block of elementary cells, for silicon this would be 1.63nm along each edge, so for a 2nm element you get a few more atoms in each direction.
That being said, direct S/D tunneling is expected to become an issue at channel lengths of around 1nm, although anisotropic carrier mass can be used to delay this further.