It seems reasonable to assume that 48-core chip is just 64-core chip with few defective cores. A lower clocked version is the same ship that high clocked that did not pass some test.
Assuming Zen 2-based Threadripper will still have quad channel memory and 64 PCIe lanes, AMD might go for a medium sized I/O die instead of disabling half of the large server I/O die. Or maybe the Threadripper volume is too low and a separate tapeout is not worth it.
If they are doing larger chiplets for Rome like 16 or 32 core but pairing up with Infinity Fabric for up to 64 cores, yields could also determine what becomes Zen2 TR with the weak chiplets becoming 8-32 core 92 chiplets), single CPU HEDT material? Or will they have a whole other solution here like limiting Zen2 TR to the same socket as previous gens to push upgrades vs a first gen TR user jumping to a Ryzen 3850X vs low end Rome?
Each of those smaller dies is 8 cpu cores. So 8x8 = 64. The 48-core one could either be 6 full-yield chiplets, or 8 partially defective ones with just 6 cores active. I'd guess it's 8 chiplets with 6 cores each just because that seems like it'd be more balanced, but I don't think we'll know for sure until someone de-lids a shipping one.
You can't do both in the same SKU because they have different performance, e.g. different amounts of L3 cache & memory bandwidth.
Epyc IO die will probably be re-used on Threadripper with chiplet slots blank though.