AMD EPYC “Rome” Server Processors to Feature 8 to 64 Cores
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But Niagara was supremely cool back then. I still have a T1000 on a rack at home (not that I use it anymore).
Good times.
Apple's relationship with Intel is pretty rocky now. Intel fumbled the i9, their Xeon chips aren't keeping up with AMD's workstation offerings, and their efforts to build a cellular modem chip utterly failed, leaving Apple at the mercy of Qualcomm for that part.
I'm sure Apple will cut loose on Intel as soon as they can. They're probably tired of the bullshit.
Yes, but I think the bigger picture, Apple needed Intel's iPhone modem for another year. May not be worth to damage the relationship, not to mention the design were likely finalise some time ago.
I would not be surprised if the Sale of Modem Business to Apple will include agreement to keep Intel CPU on Mac. ( For the time being )
And I am sure AMD should be aiming EPYC at the Datacenter usage of Apple, which is huge in itself, rather then the market of Mac Pro. Although Apple using AMD on Mac would be a pretty big statement to the rest of the market.
Also, AMD is only recently been a performance front runner - they might not hold on to that for long. In the short term it doesn't make sense to jump ship.
For for general computation/ecosystems or for generation/device specific ventures (e.g. Consoles) it makes sense to turn with the tides.
It's in Apple's history to be able to move on from hardware. It's also in their history to make the wrong choices, necessitating the move.
What if the high-end chip was ARM? It's not just about raw speed, it's about how much performance you can squeeze out of a particular thermal envelope, or compute per watt. If ARM offers 2x the performance per watt, doesn't matter what Intel's chips do with hypothetically unlimited power.
The only company that has the rights to do both ARMv8 and amd64 is.. AMD :)
It might be more feasible now, except in the last ~5-10 years there's been a push to make many PC apps x86_64 only (e.g. Ubuntu dropping i386 support), so the benefit isn't quite as wide any more.
From 2017 https://arstechnica.com/information-technology/2017/06/intel...
Extremely unlikely, if only because x86-64's memory model is much stronger than ARM's. Emulating that on ARM would be a performance disaster.
Apple could have the internals of A14 or A15 have x86's memory model, but that's non-trivial changes and may have too much impact on their ARM performance to justify it. Seems far more likely we'd just see a Macbook that's just straight ARM with x86 code just not supported at all.
> What if the high-end chip was ARM? It's not just about raw speed, it's about how much performance you can squeeze out of a particular thermal envelope, or compute per watt. If ARM offers 2x the performance per watt, doesn't matter what Intel's chips do with hypothetically unlimited power.
For workstations it's almost entirely about raw speed. The power cost is a rounding error compared to the salary of the person using it that's now spending more time waiting on things and less time getting work done.
We'll know for sure when the product is actually out and we have independent benchmarks, but at this point you're just making things up and stating them as facts.
That aside Epyc was already ahead on real high-end workloads like povray or NAMD ( http://www.ks.uiuc.edu/Research/namd/ ). Epyc also puts up top numbers on compilation performance and OpenSSL. So it already isn't as black & white as you're pretending anyway. MySQL/DMBS is not the only server workload that exists, even though it may be the only workload you specifically care about.
DBMSs are normally IO constrained or memory constrained, or lack-of-index index constrained or query-plan-gone-mental-from-cardinality-misestimation constrained, or others. It's very unusual IME to find one that is CPU constrained. Bringing up DBs in this context is peculiar to say the least.
I've literally just lost 20 hours trying to debug a query that intermittently ran many times too slow. It was a memory misconfiguration. Extra CPU is at best a bandage over these kinds of problems, at worst, just wasted.
And the successors to Cascade Lake seem to switch to the LGA4189 socket to support 8 memory channels (Cooper Lake and Ice Lake), so I wouldn't expect any upgrades on LGA3647.
The good news is that the next generation Mac Pro will have a ton of extra memory bandwidth.
However, Zen 2 Threadripper would likely be a better fit for a workstation such as Mac Pro as it will (most likely) have higher clock speeds. The current Threadripper lineup doesn't support more than 256 GB RAM, though. I don't know whether the new Threadripper will support RDIMM/LRDIMM to compete with Xeon-W on memory capacity.
https://www.asrock.com/mb/AMD/X570%20Taichi/#Specification Supports an add-in card (connector). It's coming more generally since Intel dropped the licensing fees for TB. But yeah, only a few AMD boards do it (without hacks).
It seems reasonable to assume that 48-core chip is just 64-core chip with few defective cores. A lower clocked version is the same ship that high clocked that did not pass some test.
Epyc IO die will probably be re-used on Threadripper with chiplet slots blank though.
Assuming Zen 2-based Threadripper will still have quad channel memory and 64 PCIe lanes, AMD might go for a medium sized I/O die instead of disabling half of the large server I/O die. Or maybe the Threadripper volume is too low and a separate tapeout is not worth it.
If they are doing larger chiplets for Rome like 16 or 32 core but pairing up with Infinity Fabric for up to 64 cores, yields could also determine what becomes Zen2 TR with the weak chiplets becoming 8-32 core 92 chiplets), single CPU HEDT material? Or will they have a whole other solution here like limiting Zen2 TR to the same socket as previous gens to push upgrades vs a first gen TR user jumping to a Ryzen 3850X vs low end Rome?
Each of those smaller dies is 8 cpu cores. So 8x8 = 64. The 48-core one could either be 6 full-yield chiplets, or 8 partially defective ones with just 6 cores active. I'd guess it's 8 chiplets with 6 cores each just because that seems like it'd be more balanced, but I don't think we'll know for sure until someone de-lids a shipping one.
You can't do both in the same SKU because they have different performance, e.g. different amounts of L3 cache & memory bandwidth.
Just my two cents.
Good job Microsoft.
Argh
Top-tier Ryzen 9 should reach "only" 32 cores on the 5nm process in 2 years.
But it might be 4-way SMP, so 128 threads...
https://www.tomshardware.com/news/tsmc-5nm-euv-process-node,...
"DIFFUSED IN USA"
What exactly does that mean? Given the next line is "MADE IN CHINA", it would seem like "DIFFUSED" should be "DESIGNED" - or does that word have a new meaning?
Made is where it's attached to the substrate, packaged etc.
(These chips do exhibit NUMA)
Edit, just confirmed:
>Thanks to this improved design, each chiplet can access the memory with equal latency. The multi-core beasts can support to 4TB of DDR4 memory per socket.
https://www.tomshardware.com/news/amd-64-core-128-thread-7nm...
So there is no longer "near" and "far". In a sense, it's all "far" now (but hopefully not too far). But it is all uniform now.
Economically, there aren't so many people looking for 1000 cores that it makes sense to put in the NRE to assemble a giant package to put all of that in versus just selling a system that can have multiple sockets. Cooling limits also make spreading out work across multiple sockets a better choice.
What's more equivalent to a CPU core would be what NVidia calls an SM and AMD calls a compute unit. These decide which instructions to issue next and broadcast them to the various lanes. You'll have dozens of them in a typical GPU, about the same as the number of CPU cores in the same silicon area.