For synthesis, the only FPGAs families currently supported by an open source flow are the Lattice iCE40 and ECP5 [0]. The latter is something you can be decently productive with and can fit quite a bit of logic (think: Amiga reimplementation, PCIe interfacing, etc.).
If you'd like to port synthesizeable code from the open source world to the commercial world, this _should_ just work as long as you're willing to rewrite any physical interfacing code (since those depend on hardware blocks available in a particular family) and stick to high-quality Verilog. But that's the same as porting across any other FPGA families.
Disclaimer: I work with SymbioticEDA, who develop and provide commercial support for some open source digital logic tooling, like Yosys and Nextpnr.