Unfortunately most of the tools used in the EDA industry are proprietary and stuck in the 90s. So it is both expensive and pretty painful to use them, although after a while a kind of Stockholm syndrome sets in. In other words you really need Cadence and access to a Designkit from a foundry in a relatively recent process (65nm TSMC, 22nm SOI Global Foundries, etc.) to implement something serious. Similar things apply to digital design, although with tools like Chisel and Verilator (system verilog to C++ compiler) you can do more things with freely available tools. Once you want to tape out your design a lot of very expensive proprietary software is still involved. It is also pretty unrealistic to do everything yourself. It is a multi year single person project to setup an understand a new analog design kit itself.
So my best advice is to find a group that has already setup most of that support infrastructure and obtained licenses for all the tools and design kits (We've got one person alone that handles licenses, software installation, and the ASIC cluster).
Ideally the group has permanent staff with plenty of hardware experience and a professor with a proven track record of successful chip tapeouts. The number of groups that are capable of this in the field you are interested in can be counted on two hands at best.
I can't talk much about analog design, because I've only witnessed people doing it and haven't done any design with them myself, but you need to be a very particular kind of person to enjoy it, especially if you have no-one to do the layout for you.
Oh and you should think long and hard if you really want to go into this direction, it involves a lot of really hard and tedious work and is not glamorous at all. A tapeout might fail because someone accidentally checked a box in the last step before sending the design to the manufacturer, removing all blackbox pins on the edge of the design. Or someone might have though that it is a good idea to put a latch in the PLL reset path, which causes the clock to never turn on, which you only discover in the back annotated simulation 5 days before tapeout.