This is also the idea behind the Pixel Planes rendering architecture from the 80's, they called it "logic-enhanced memory chips". It's not a "universal CPU" on the memory chips, but each chip can "process" and store 128 pixels, where the processing is implemented with a hardwired linear expression.

Here's a video on Pixel Planes 4 from 1987:

https://www.youtube.com/watch?v=7mzpZ861wEw

Of course when you start to look at how much die space is dedicated to SRAM on current CPU's, you begin to realize in a sense we have this now.

Convergent evolution.

There's still some research on this general idea -- e.g., a fellow grad student's work on in-memory bulk data operations:

- https://archive.org/details/arxiv-1611.09988 (AND/OR/NOT in RAM)

- https://www.pdl.cmu.edu/PDL-FTP/NVM/rowclone_micro13.pdf (cloning data in RAM; full disclosure, I'm a co-author on this one)

And IIRC at least one start-up (Emu Technology) that has built actual processing-in-memory (PIM) hardware.

Berkeley IRAM

still a good way good way to get your phdce in computer architecture at least according to a couple profs i've talked to