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Comment by timerol | Hacker News Reader

This talks about two major performance concerns in CPUs: control flow and memory access. The transition between the two was my favorite part of the article. It's both funny and accurate.

"If the previous section gave the impression that, say, control flow is a particularly tough problem, but inventive methods can give powerful and practical tools to tackle it… good, that was the intent. In this section I want you to take that expectation and dash it against the rocks — memory is hard."

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In the 90’s there was a group experimenting with putting small processors directly on the memory chips and doing data processing there.

Berkeley IRAM

This is also the idea behind the Pixel Planes rendering architecture from the 80's, they called it "logic-enhanced memory chips". It's not a "universal CPU" on the memory chips, but each chip can "process" and store 128 pixels, where the processing is implemented with a hardwired linear expression.

Here's a video on Pixel Planes 4 from 1987:

https://www.youtube.com/watch?v=7mzpZ861wEw

Sounds rather similar to GPU architecture.

Pixel Planes is the ancestor to GPUs with the identical relationship of the titans to the gods in Greek mythology.

There's still some research on this general idea -- e.g., a fellow grad student's work on in-memory bulk data operations:

- https://archive.org/details/arxiv-1611.09988 (AND/OR/NOT in RAM)

- https://www.pdl.cmu.edu/PDL-FTP/NVM/rowclone_micro13.pdf (cloning data in RAM; full disclosure, I'm a co-author on this one)

And IIRC at least one start-up (Emu Technology) that has built actual processing-in-memory (PIM) hardware.

Of course when you start to look at how much die space is dedicated to SRAM on current CPU's, you begin to realize in a sense we have this now.

Convergent evolution.

Maybe we should just go NUMA and address the on die “cache” directly.

still a good way good way to get your phdce in computer architecture at least according to a couple profs i've talked to

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