Wow, I get frustrated and feel unproductive if my feedback loop is longer than 2-5 SECONDS. This must require a seriously different approach to trial and error exploration
The full build to a bit file that can be loaded into hardware is an NP-hard optimization problem, so as your design approaches the limits of either the desired clock speed or the amount of space in the chip, it can become very slow.
Placing (not routing!) takes around 24 hours since we need to run in a larger environment than just the block level to get realistic timing reports