I wish the author had explained how he went from identifying that the issue is stalled references to DRAM to the CYCLE_ACTIVITY.STALLS_L3_MISS performance event. Similarly from DRAM_Bound to MEM_LOAD_RETIRED.L3_MISS_PS. My complaint is that there's still a lot of magic here that requires carefully reading the Intel manuals that is elided in this post. That said, thanks to the author for the post---it is still very useful.

Edit: the author has another post that covers this information https://dendibakh.github.io/blog/2018/06/01/PMU-counters-and...