Top-down performance analysis methodology

A note here that "front end" and "back end" are meant in the CPU microarchitecture sense, not the web development sense.

I think Brendan Gregg's Systems Performance: Enterprise and the Cloud is still the single best volume on this topic; I'd recommend Gunther's Guerilla Capacity Planning as a useful followup to get a foothold on theory.

I wish the author had explained how he went from identifying that the issue is stalled references to DRAM to the CYCLE_ACTIVITY.STALLS_L3_MISS performance event. Similarly from DRAM_Bound to MEM_LOAD_RETIRED.L3_MISS_PS. My complaint is that there's still a lot of magic here that requires carefully reading the Intel manuals that is elided in this post. That said, thanks to the author for the post---it is still very useful.

Edit: the author has another post that covers this information https://dendibakh.github.io/blog/2018/06/01/PMU-counters-and...

Would play nicely with the Scalability Prediction tools we built: https://stacktical.com/demo As soon as a regression is detected in the CICD pipeline a Top-down analysis can be done to according to the amount of Serialization and/or Synchronization penalties.

Would love to see the exact same thing but for ARM, and in particular aarch64.