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Comment by ris | Hacker News Reader

Really? Does RISC-V have delay slots? To me, this is one of the biggest differentiating factors in ISAs.

Delay slots are generally regarded to have been a mistake since they link the ISA to the physical implementation of the processor too closely. That means you end up paying in speed and complexity for architectural choices of past processors in your future processors. RISC-V was designed to be a modern architecture informed by the mistakes of the past.

No the specifically removed it. The RISC-V guys at Berkley said that all their high performance implementations had always major problems with delay slots.

Yeah, having dispatch order not match retire order is a huge pain in the ass for OoO cores.

Can you not make delay slot a dependent item to retire?

There's a lot of ways around it; there's been several MIPS OoO cores.

It's just a pain and adds complexity to exactly the parts that are hardest to get right as it is. For instance the state unwinding on hardware exceptions and the like.

I believe the parent meant that to go under the "less legacy baggage" heading.

IIRC nanomips(?) doesn't have delay slots either?

nanoMIPS doesn't have delay slots IIRC. microMIPSR6 also deprecated delay slots for branches. MIPSR6 got rid of delay slots for a family of branches called 'compact branches' which have 'forbidden slots' which require that back-to-back branches be separated by a nop or other instruction.

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