Hacker News Reader

Comment by IntelMiner | Hacker News Reader

I've heard a lot of people say RISC-V is very "MIPS Like" as well

Just minus a lot of the "legacy baggage"

RISC-V's integer multiplication extension doesn't do the lo/hi trick MIPS did, and it doesn't specify a latency; that is, the integer multiplication opcode, if your chip has one, returns its value in a normal register, not split into a special lo register for the low bits and hi for the high bits, and it executes in a normal sequence with the others from a software perspective, as opposed to MIPS, where it was specified to execute sychronously with the normal instruction stream, and you'd only stall the pipeline if you tried to read lo or hi too early after the mutiplication opcode had issued, before the actual arithmetic was completed.

https://stackoverflow.com/questions/27893526/mips-are-some-a...

> Programming Notes:

> In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel. Programs that require overflow detection must check for it explicitly.

> Where the size of the operands are known, software should place the shorter operand in GPR rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

(MIPS32TM Architecture For Programmers Volume II: The MIPS32TM Instruction Set, mul / mult instrutions)

It's... a bit more low-level than assembly ISAs are typically designed to be these days.

FWIW, if I had to pick the "biggest differences from MIPS" in RISC-V, it wouldn't be the fact that MUL works on GPRs.

More important is the lack of a branch delay slot (i.e. it doesn't bake in a particular pipeline stage design into the ISA), and the existence of hardware paging (MIPS tried to cheat here by letting software handle page faults, and in hindsight made a poor decision).

MIPSR6 does away with the HI/LO registers and have multiplication instructions which return the result to GPR registers.

Pre-R6 MIPS cores have the MUL instruction which hide the usage of the HI/LO registers, but do clobber those registers.

That is mostly true many of the early RISC share a very common base as most of these people were sitting on top of each other. Sun nearly hired the MIPS guys but they went of and did their own thing so they did SPARC.

However it would be wrong to say it just, removed baggage, it also has and will add a lot of interesting ideas.

They also spend a lot of time fiddling with details, how small you can make the decoder, op code layout for a modular design, how to avoid backing micro-architecture decisions into the ISA.

Really? Does RISC-V have delay slots? To me, this is one of the biggest differentiating factors in ISAs.

No the specifically removed it. The RISC-V guys at Berkley said that all their high performance implementations had always major problems with delay slots.

Yeah, having dispatch order not match retire order is a huge pain in the ass for OoO cores.

Can you not make delay slot a dependent item to retire?

There's a lot of ways around it; there's been several MIPS OoO cores.

It's just a pain and adds complexity to exactly the parts that are hardest to get right as it is. For instance the state unwinding on hardware exceptions and the like.

I believe the parent meant that to go under the "less legacy baggage" heading.

IIRC nanomips(?) doesn't have delay slots either?

nanoMIPS doesn't have delay slots IIRC. microMIPSR6 also deprecated delay slots for branches. MIPSR6 got rid of delay slots for a family of branches called 'compact branches' which have 'forbidden slots' which require that back-to-back branches be separated by a nop or other instruction.

Delay slots are generally regarded to have been a mistake since they link the ISA to the physical implementation of the processor too closely. That means you end up paying in speed and complexity for architectural choices of past processors in your future processors. RISC-V was designed to be a modern architecture informed by the mistakes of the past.

Reply on news.ycombinator.com