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Comment by praptak | Hacker News Reader

My friend studied chip design and was taught how to design for planned failure after X years, curiously without any ethical considerations. Are these techniques actually used in practice?

(That was my first thought after reading 'death by design')

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I work in chip design, and we certainly don't design for planned failure, but we do design for 20 year reliability. This means we over-design to ensure reliability up to 20 years. If a market does not need such longevity then it would be reasonable to design for less time, to ensure you are not over designing. Chip deign is all about trade offs - power, area, performance, reliability, flexibility, integration cost, high/low temperature operation, yield, etc - and designing for 20 years certainly impacts this trade off.

What's the upper limit of longevity testing, say for space use, 100 years ?

Good question, it depends on a few factors - e.g. BTI is aging that alters the transistor performance over time when a transistor has a fixed bias, so if you've loads of margin for this it should not impact you, or you can mitigate by periodically altering the bias to recover. TDDB is an issue at higher than normal voltages, so of the environment is controlled this can be avoided. For high reliability situations older process nodes are usually used which are less susceptible to these failures, and the environment is well controlled. Space has other issues like much higher probability of random bit flips, so design for space is challenging. Note our 20 year lifetime also assumes worst case conditions, so I'd wager many of our chips would last much longer in practice.

What does changing the bias to recover look like in practice? Any resources on this?

I'm not sure about resources but I can explain the basics. BTI happens when there is a constant voltage across the gate/source of a transistor for a long time. An example for a digital circuit could be an inverter held in one state. Either the pmos or nmos will have a large vgs and over time this bias will shift the threshold voltage (vt). Now if this inverter delay is critical, BTI will cause the delay to change and could break timing. To fix it if the inverter is toggled after sometime it will mostly recover to the normal delay. Some people mitigate it by having very low frequency toggling for 'off' gates, but usually only if those gates are critical/matched. Alternatively people just margin the timing for the worst case. Analog circuitry has to be designed for it also, and it's an issue in differential pairs for example.

There's another issue - metastability - in some designs with multiple clock domains it's not possible to create absolutely reliable chips - things fail (dynamically, usually without any damage to the chip though there's actually a minute chance of runaway power eating cascades of failure, something we try to avoid).

For example the graphics back end of a video card is running its framebuffer memory at a different clock rate from the video dot clock, at some point pixel data has to move from one clock domain to the other - metastability failure might cause an occasional bad pixel on the screen, you can do the math, trade latency (and more gates) for reliability so that you see that pixel burble once a year.

Other times it could be worse - I worked on a chip where we did the math on whether the PCI interface would suffer synchroniser failure and what the worst case failure was (maybe bus lockup?), in the end the boss signed off on once a year ... which at the time was ~100 times the mean Win95 uptime

So we do sort of do that math, knowing that you can't 'fix' metastability issues, just make them rare

It's not designed for failure at point X, it's designed for proper operation until at least point X. You always add some safety margins such that the failure rate in the designed life is low enough. After that most of the devices may still work for a long time.

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