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Comment by mankash666 | Hacker News Reader

Much Ado about nothing - Intel furnished modem on the iPhone uses x86 instructions!!!

the news is that intel has competitive modems .. would have never expected that

to me the news is: intel has competitive modems that use intel instructions

were they used often in the recent years regardless of the arch of their modem chip ? it's been long since I heard their name.

Yes, Intel has been a baseband chipset on iPhones for a while now (at least since iPhone 7, can’t remember if earlier), just not exclusively.

Edit:

And as the original iPhones used Infineon chips (which Intel acquired), depending on your perspective, you could twist it and say they’ve been there since the beginning. Bit disingenuous to me, but I could see someone making that claim.

Well it's a battery powered phone. Decoding x86 instructions and converting them to the processor's internal microcode, unless it's not really the full x86 ISA, is not energy efficient. This means there may be a noticeable battery life difference between the GSM and CDMA versions of the new iPhone.

> Decoding x86 instructions and converting them to the processor's internal microcode, unless it's not really the full x86 ISA, is not energy efficient.

That's a very antiquated view of modern CPU design. Unless you're designing a coin-cell powered CPU the x86 decode stage is effectively free and can be disregarded. Besides: most ARM (and nearly ever other modern RISC CPU) does the same thing, decoding the instructions to internal micro-ops. x86 variable-length instructions vs RISC multiple instructions can be thought of as different instruction compression schemes and which one treats your L1-I cache better depends on workload.

CPU ISAs are effectively an ABI for hardware. Except for the extremely low end, no one directly executes the ISA anymore and hasn't for years.

I suppose if anyone were designing new ISAs they'd design them with that assumption, to avoid baking-in temporary implementation details they'd regret later (see: branch delay slots).

> I suppose if anyone were designing new ISAs they'd design them with that assumption, to avoid baking-in temporary implementation details they'd regret later (see: branch delay slots).

Yep. See RISC-V's decision making process.

So does IBM Power.

There's some gross dark corners in Power. Their page table format is the stuff of angry elder gods. Additionally the shared CR register is a complication on OoO cores.

Those benefits are really over stated. Even the slightly bigger RISCs will convert into internal micro-op for various reasons generally. You can even see this openly in the RISC-V BOOM HDL.

All the new phones use the Intel modem...

numbers please

This is literally the reason all mobile devices run on some variant of arm or mips, and why umpc's from the 00s never really caught on.

There are some Android devices that use Intel Atom, so it's not quite right to say that "all" devices use ARM or MIPS.

Wait what. Where is this article suggesting conversion of x86 to arm assembly prior to execution? Stop making things up. Unless otherwise proven, it's x86 executable running on x86 intel cores within the modem or related compute.

I don't read anything of the sort in his comment.

Then you don't read right. "Decoding x86 instructions and converting them to the processor's internal microcode ..."

Modern x86, for the past 25 years or so, doesn't implement the instructions directly. There's an internal intermediate, proprietary reduced instruction set. So outwardly it's a cisc processor, with variable length instructions and a lot of different instruction modes, but internally it's not.

And even before then they decoded in microcode. That goes all the way back to the 8086, which had five banks of microcode IIRC.

Speculation about how an embedded x86 works. Just because their desktop focused, non-power optimized products do something, doesn't necessarily mean their embedded line-up does the same.

FYI - Apple is a hard driving customer, they do not compromise on power, performance & cost/pricing

Every x86, from 8086 on, has been microcoded.

Well, you're up against basic physics here: bigger die required to decode full x86 ISA, more power, more heat.

But a 486dx with more integrated cache could be incredibly efficient with modern manufacturing processes. A modern i5-8250 uses under 15W power... we're talking something less than 1/1000 the complexity.

The parent comment never mentioned ARM. Modern x86 CPUs translate instructions to non-x86 internal microcode.

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