If my memory of a Processor Design course is correct, arranging the desired functionality onto the finite resources of an actual FPGA chip, let alone in such a way as to get good performance (i.e. have critical paths be as short as possible), reduces to bin-packing.
The answer might be obvious, but I'm not a hardware guy: couldn't they use a FPGA to do the compilation itself, or at least the bin-packing part? Is there a way to code a general SAT-solver in FPGA?