A Thunderbolt controller contains a Converged I/O switch (CIO) plus a PCIe switch. The Downstream Ports on the PCIe switch are attached to the CIO switch and represent so-called PCIe adapters which encapsulate PCIe datagrams into Thunderbolt datagrams.

The PCIe throughput is thus the minimum of the CIO switch's capacity, the PCIe switch's capacity and the PCIe adapter's capacity. The PCIe 4 lane interface is only how the Upstream Port on the PCIe switch is attached to the CPU or PCH.

It is very unlikely that Intel will answer this question satisfactorily because they'd reveal details of the controller's internal architecture.

Note that a PCIe tunnel may pass through a Thunderbolt controller without being terminated on it. The CIO switch must then handle that tunnel's traffic in addition to any tunnels terminated on it.

(Disclosure, I've authored a couple of commits in the Linux kernel's Thunderbolt driver.)