What is Intel’s Thunderbolt 3 dual port controller’s total bandwidth?

Thunderbolt, and Intel's "management" of that interface spec, is an excellent contrasting example of IEEE interfaces vs closed systems. I actively worked on a project building around TB2 (and then 3) for over two years and eventually we gave up on the entire thing due to the obscurity of the protocol, the absence of details of the Intel implementations (the only game in town at the time), and a myriad other roadblocks. By contrast I have some historical familiarity with Sony's Firewire iterations and once it became IEEE-1394 (and variants) it exploded in both popularity and transparency.

If Intel treated the original USB in the same way they do ThunderBolt, we'd still be using ADB, serial, parallel, and PS/2 interfaces on all our machines.

> Thunderbolt* is customized by each system manufacturer differently on their platforms. For this reason, our recommendation is that you can contact your system manufacturer to receive accurate information about their products the Thunderbolt* 3 implementation.

This means ask your system manufacturer to give the bad news.

Thunderbolt is a quite under-documented protocol. I realize it's proprietary (for now) but even by those standards there is almost nothing publicly available. Maybe Intel doesn't want people to know that a dual-port "40 Gbps" Thunderbolt controller only has 32 Gbps of PCIe bandwidth total and according to this question each port only supports 22 Gbps. This may explain why real-world benchmarks don't show performance anywhere near 40 Gbps (although TB3 is generally still faster than any other consumer protocol).

A Thunderbolt controller contains a Converged I/O switch (CIO) plus a PCIe switch. The Downstream Ports on the PCIe switch are attached to the CIO switch and represent so-called PCIe adapters which encapsulate PCIe datagrams into Thunderbolt datagrams.

The PCIe throughput is thus the minimum of the CIO switch's capacity, the PCIe switch's capacity and the PCIe adapter's capacity. The PCIe 4 lane interface is only how the Upstream Port on the PCIe switch is attached to the CPU or PCH.

It is very unlikely that Intel will answer this question satisfactorily because they'd reveal details of the controller's internal architecture.

Note that a PCIe tunnel may pass through a Thunderbolt controller without being terminated on it. The CIO switch must then handle that tunnel's traffic in addition to any tunnels terminated on it.

(Disclosure, I've authored a couple of commits in the Linux kernel's Thunderbolt driver.)

Level 1 Techs does a great video on getting Thunderbolt via USB-C working on Ryzen Threadripper. You can run Thunderbolt on Threadripper, but not Ryzen 7.

https://www.youtube.com/watch?v=uOlQbP63lDQ

I think the reason this question so so hard to answer for Intel is because Thunderbold on Intel goes through the chipset, after which it's on a shared PCIx4 lane to the processor. The main reason for this is hotplugging PCI-E is difficult.

On Threadripper, the Leve1Tech use a lot of hacks to get an Intel Thurnderbolt controller connected directly to the PCIE lanes that go straight to the processor.

The first response posted is absolutely hilarious and perfectly summarizes basically every educated person's attempt to get tech support from any large company.

AFAIR Intel alway is like that. Intel hardly open their documentations to the public because they only communicate with big PC/motherboard manufacturers, not individuals.

Intel did the same thing to hobbyist communities when Intel tried to enter consumer IoT market with Arduino101/Edison/Curie. They did open sourced the code (more than a year late since released the hardware though) but never provided good enough public documentations about the chips. Intel eventually gave up the market.

The answer is, it depends. PCIe is not a streaming interface, so the effective bandwidth depends on transaction type, latency, packet size, address depth, etc. etc. The only certainty is that it will not be anywhere close to 32gbps, that is line rate.

I'm still pretty disappointed that AMD's alternative to Intel's Thunderbolt, which I think they called something like "Lightning Bolt", never went anywhere. It struck me then as a cheaper open alternative which could do most of the things people would really want to use Thunderbolt for but without the costs.

Meanwhile, the bandwidth of a single-port 9-pin Atari controller is almost well understood.

What if they told you their products are so fast they don’t need a total bandwidth?