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Comment by etaioinshrdlu | Hacker News Reader

I have programmed for the same c674x chips they mention as doing machine learning ... Let's just say the have a mere fraction of the FLOPs that a nvidia GPU or other "AI" processor would have.

Granted, good machine learning is not all about compute power, and you can certainly do interesting things with less power. But this is not bleeding edge deep learning for sure :)

On the other hand, TI is a company you can actually count on to work with you to be able to build a product that can be verified to be dependable, in a mission-critical, hard real time sense. TI open sources most of the software stack.

NVIDIA, well, not so much. I've run into serious issues with their binary blob drivers and their engineers have a rather DGAF attitude about the whole thing. Secrecy and bluster are the name of the game. Torvalds' opinion on the matter rings true.

TI just seems friendlier and less cutthroat. Their support of the BeagleBoard etc is telling.

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I had to register to comment about TI "quality" and friendliness ;-).

Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktdma will hang if you will use chained descriptors but you will not find it in silicon errata. TI response was - "just don't use it" and refused to verify it on their side.

The ISA of c66x DSP is just stupid - you have quad SP multiply but only double SP addition - forming registers back and forth in quads will result in MV instructions often (because compiler is not so smart). There are no real vector registers, "vector" instructions take 4 or 2 32bit registers.

Want to compute power of individual complex int16 in a vector ? You are out of luck - DDOTP4H will add everything together.

There is even no way to utilize their multipliers fully since load&store is 2x64 bit, while multiplier can perform 8 SP multiplies per cycle.

Moreover memory access to L2 is so slow that you will wait in memory stalls (there is no HW prefetch from L2 to L1D cache) and L1 SRAM is way to small to do anything serious (32 kB).

After trying other DSPs, like CevaXC or VSPA, TI looks like poor joke. Their C7000 that supposed to address some of those problems is long overdue and will be well underpowered comparing to recent Ceva DSPs or NXP VSPA.

Also good about TI is they are far more willing to have a long term commitment to a particular chip or other component which is a must when you're designing something that you want to market for at least a couple of years.

There is nothing more irritating than to finalize a design for manufacturing and being hit with an EOL'd part with some ridiculously short deadline.

You end up with having to choose between to really bad choices: stock up as many parts as you can risking ending up with unused inventory (and still a fair chance of running out on the other end) and redesigning the product.

Yeah, you don't want to do AI in DSP, but signal processing yes.

There's a lot of work between reflecting radio signals and having a "radar image" that can be fed to AI systems, and that seems to be the main target of the dsp.

You certainly won't want to train on a DSP, but running them shouldn't be too much.

I too have nothing but great things to say about TI.

Would it be plausible to train slowly on a DSP, if the data is also being collected slowly, at the edge?

By the time you have a reasonable dataset, you've also had a reasonable amount of training... of course, with only a little training on the complete dataset.

Depends on your model - in the majority of cases training is a separate act from using the model, and just because you trained it doesn't mean it's well fitted. You end up caring about training speed because you don't know how many training runs you may have to do, grumpily fiddling with the model and hyperparameters after each training session trying to get a good model. Technically possible but probably not practical

Indeed, it is a shame that so harmful to the industry company like an NVIDIA became a leader in Machine Learning. Hopefully it will change soon enough.

I'd say the fault lies with the community for choosing the proprietary Cuda instead of open cross platform alternatives.

I think part of the problem there was that more courses were taught with CUDA than OpenCL. That put a dent in OpenCL's popularity

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