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Comment by BeefySwain | Hacker News Reader

My understanding is that all these have in common with RAM is sharing the DIMM connector. There are a number of technologies that use DIMM connectors that are not RAM, for example, the Raspberry Pi Compute Module[0] uses a SO-DIMM connector to save space and money by not having to break out IO nor provide any sort of connectors.

[0] https://www.raspberrypi.org/products/compute-module-3/

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It's not just the connector. The electrical interface is DDR4, and it's accessed through the CPU's DRAM controller as part of the existing memory hierarchy. It's just that the memory addresses corresponding to the Optane DIMMs will be slower than the addresses corresponding to DRAM.

New CPUs will be required, and if there's a technical justification for that it will probably be that accessing an Optane DIMM requires timings that are far outside the normal range for DRAM modules that the existing memory controllers were designed to accommodate.

It's also integrated to new instructions to flush things and wait for them to be made persistent.

Intel actually backed off on those plans, and now any regular cache flush will suffice. There are still some new cache flushing instructions, but they merely offer performance enhancements, not stronger memory safety guarantees.

https://software.intel.com/en-us/blogs/2016/09/12/deprecate-...

Does this mean that, with a DIMM-to-LAN interface and cloud storage backing, one could literally download more RAM from the internet?

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