Hacker News Reader

Comment by ai2323 | Hacker News Reader

Welcome to ASIC land....training going the route of crypto mining

It's just an arithmetic logic unit for tensors. It's not at all like a crypto miner that implements a single algorithm.

You kind of summed it up right there...'it's just an arithmetic logic unit for tensors'...whether its a matrix multiply engine or implmenting sha256 still a custom rapidly iterated chip for narrow very specific use case. Google accomplishment here clearly the software, but doubt they only ones going to crack asic systolic arrays. At some point china inc figures this out in mass...maybe bitmain themselves.

Bitmain already announced TPUs (cue "they'll only sell them after they're finished training Skynet").

FYI, here is Bitmain's AI product homepage: https://www.sophon.ai/

They shipped Deep Learning Accelerating Card SC1 at $589. You can't buy it right now because it is sold out.

Well... I'll concede that 2-instructions that aren't reading or writing memory is a pretty narrow set of operations. But it's also much more generally useful than computing one specific hash function.

Completely agree with you there. Guess the analogy I was making was more about the evolutionary speed we saw there. Google seems to be moving awful fast here.

Faster matrix multiplication is something which has application in practically every engineering field there is.

Exactly. Drives me crazy when people compare to a single alogrithm chip. It is not.

But the TPU actually is: it's a systolic array matrix multiply ASIC.

The TPUs support all kinds of NN. Not specific to one type.

Indeed, all neural nets that use matrix multiplication. Out just so happens to be all the main types right now.

Google is the leader on AI algorithms. Where GANs and Capsules and so many others came from for example. So things change and Google can implement in silicon far earlier than anyone else as needed.

But right now they have what they need.

BTW, I would be curious on the TPU 3 design considerations to better support dynamic routing with Capsule networks. I suspect creates different memory access patterns and where the big power savings are at today.

You are constantly comparing this single-purpose chip to a general-purpose GPU. How is that any different?

Reply on news.ycombinator.com