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Not sure what you mean, I can process non-cached sequential data from RAM over 20 GB/s by using SSE/AVX.

There's no chance you could achieve same by using scalar instructions. SIMD can access memory a lot faster than scalar.

Random access is another matter. The trick is of course to avoid non-sequential access patterns.

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Isn't the bottleneck in any sequential access case the memory bandwidth?

IOW: Are the scalar instructions slower than memory bandwidth?

you can saturate memory bandwidth without SIMD, since you can issue at least 2 8-byte scalar loads per cycle. it does not leave much room for actual processing though

Isn't that just a prefetcher win? AVX/SSE lets you do more computational work per cycle but I don't see how it would improve memory bandwidth/access.

The CPU's load/store unit is usually designed with SIMD in mind, and the access width is 16 bytes (or 32 bytes for Haswell-and-later Intel CPUs). This means you get more bandwidth by using SIMD.

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