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Comment by robin_reala | Hacker News Reader

This reminds me of delay line memory, storing information in the echo of a sound: https://en.wikipedia.org/wiki/Delay_line_memory . LEO had long tubes of mercury for this, not sure I would have wanted to work in that office.

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I think very few bits here are actually stored in-flight on the copper/fiber/radio at any time. Most of them are probably stored in various buffers of networking equipment (which are ordinary semiconductor RAM). It would be interesting to see someone do an actual breakdown for, say, a transatlantic link.

My gut feeling says that only geostationary satellite links have any significant number of bits in-flight.

Very simplified, but assuming a 5000 km cable and 300 000 km/s speed of light (is slightly slower in fiber), light needs 0.01666... seconds for that. At 10 Gbit/s (fairly slow), that'd mean ~ 166 Mbit or ~ 20 Megabyte in flight. (I hope I didn't forget a factor 1000 somewhere)

Your calculation makes sense. However, for those 20 MB in flight, how much data is stored in buffers? I think that could be approximated by comparing ping time with speed of light.

e.g. if a 5000 km long link at 10 Gbit/s has latency of 0.0166 s, then you have zero buffering. If you have latency of 0.2 s, then around 2 Gbit of data must be stored in buffers somewhere, making 20 MB in flight only 1% of all data stored in such a ping filesystem.

How about the earth-moon-earth path for 768,000km?

EDIT: For the EME path that's around 3 gigs in flight

We've found a viable way to a space elevator: Sell it as a delay-line storage device.

In a small toroidally shaped universe, your radio is also your memory. All emissions eventually return to their origin, but you can reorder memory transmissions by moving while the data is in flight.

Same principle, but using slabs of glass, was used in PAL analog color television until digital memory got cheap enough to implement the delay line.

Actually, Engineering Research Associates (predecessor of Univac) built a CPU with mercury delay line memory using acoustic transducers to create a shift register. It did bit-serial binary arithmetic. You could get two logic gates or one latch out of a dual pentode, so a bit-serial ALU could fit easily in a single rack.

I'm not familiar with the overall architecture, though, unfortunately. I do remember having to do a most-significant-bit first, bit-serial, two's complement adder as a homework assignment that was inspire by the machine.

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