Hacker News Reader

Comment by Waterluvian | Hacker News Reader

Oh god. Their versioning system uses a unit of measurement that is decrementing towards zero. Those poor souls!

At this point a measure based on some number of average gates per square millimeter (won't that be fun to get everyone to agree to) would be better advertising, and more truthful.

Working on an areal density works better in an era where improvements are going closer to linear.

Aren't transistor densities vastly different for DRAM cells and logic? So you must choose what kind of stuff it is before "gates per mm^2" makes sense, no?

why not just use more millimeters. if you don't invest $BNs in making smaller dies you can just sell bigger chips. and also charge more for a BIGGER and BADDER chip every year. then when it gets out of hand use a smaller process intel has abandoned already.

Heat.

cooling technologies have also moved forwards too. a stock water cooler block instead of a fan could solve that.

Price is proportional to die size. Processing one wafer is a fixed price, so the more chips you can fit on one wafer, the cheaper each individual chip.

Additionally, the number of defects is proportional to the area. The bigger your chip, the more chips you will have to throw away because of defects. E.g. say you have one defect per wafer on average, if your chip takes up the whole wafer, you will have no good chips. If you can fit 100 chips on one wafer, you will have 99 good ones and one bad one.

yes, i'm aware. but i'm sure the "processing cost" also factors in R&D to get to that node size up to that point.

you also don't need to double the die size just double the size of the package (what AMD seem to have done), that way you can swap broken dies out.

Correct me if I'm wrong, but I don't think AMD physically swaps out defective cores. I believe they're disabled individually in some kind of firmware. That's effective because the interconnect region is significantly smaller than the core area (and possibly made more reliable through feature size manipulation?). I think this has been standard practice almost dating back to multi-core introduction, where they sell high end multi-core chips as low end with some cores disabled.

Note parent was talking about die and not cores.

AMD are shipping multi-chip modules with ThreadRipper (with two die) and EPYC (with four), and then because they are separate die you can trivially swap them out.

i believe this is a way for them to maximise yield, say their threshold is at least 3 dies must be good, and only 1 can be passable, then when they do tests and only 2 are good, they can swap out one of the passable ones, they can also rate the cpus differently too, they could also just swap out dies when all fail the test, i.e with threadripper and replace with another 2, then rate those.

Different types of gates use different amounts of silicon area. Combining gates "cancel out" different number of transistors. So the gate density you'll end up with also depends on your specific application.

I think the number of transitors per unit area would be better. Though advanced applications mess with transistor sizes too, the situation would be better than gates.

They can just switch to picometers whenever it gets really dumb.

They already had to do it once, from micrometers to nanometers.

The closest distance between silicon atoms in a crystal is about 235pm, there's not much room with picometers for processor design.

How do you even pass electrons through a line 6 atoms wide... :S

Something like mixing legos with 3d printing and quantum mechanics.

https://www.nature.com/nnano/journal/v7/n7/full/nnano.2012.9...

https://en.wikipedia.org/wiki/Single-atom_transistor

They must feel like Urbit users.

Maybe they can adopt an exponential versioning system. Just decrease by a power of ten every revision.

Reply on news.ycombinator.com