Hacker News Reader

Comment by jacquesm | Hacker News Reader

The step from 14 to 10 nm is huge. Both from a technological perspective on the manufacturing side as well as on the effect it will have to the number of transistors on a die and the power consumption of those transistors. Remember that power consumption and the number of transistors are related to the surface area so there is a square factor in there. 14 nm ^2 = 196, 10 nm ^2 = 100, so that's almost a doubling of the number of transistors and approximately a halving of the power required per transistor for a given die area.

View on HN

Okay, so the node names are effectively useless at this point. They used to refer to gate length, but no longer, even for Intel. Oh, and Intel's 10nm will actually have lower performance than their 14nm.

Besides, it matters not, the bottlenecks today are in memory and interconnects.

> Oh, and Intel's 10nm will actually have lower performance than their 14nm.

Less than 14++, sure, but 10+ and 10++ will fix that.

Yes, but I was just pointing out that scaling is now neither a panacea nor free.

Performance compared to what? Same power, Same price, or just the performance of the fastest processor of the series?

At some point, maybe we'll start seeing RAM put onto the CPU itself.

I mean, more than it already is (with cache).

You will see stacked memory and silicon interposers, but you won't see main memory on the CPU die. DRAM is based on an array of what is called "trench capacitors." The fabrication process is sufficiently different that they don't even make these in the same facility, much less on the same die process. An array of trench capacitors will always be smaller than transistor based memory (SRAM.)

There are alternatives on the horizon, e.g. STT-RAM, MRAM, memristors, PCMs, ReRAM (same as memristors according to some...), spintronic devices, etc.

There are also other attempts such as FBRAM to replicate DRAM structures without the need for insane A/R trench capacitors.

I believe that such solutions are necessary to continue scaling.

It is not a big problem to make DRAM on pretty much every SOI process, just power consumption and refresh rates will have to be quite big.

The problem with MRAM is unreliable reads, they are excellent for low clock speed devices, but as you go into gigahertz range, signal quality of an mram cell begins to degrade, and you have to put a darlington on top of it, or a bicmos transistor, thus negating its cell size advantage

For DRAM are you talking about standard deep tech capacitor dram or FBRAM?

Agree with MRAM, but it is also a very immature technology, so there's hope at least. unless you're talking about crossbar crosstalk which can be solved with a diode.

About floating body ram and others that rely on capacitance of the substrate itself rather than a dedicated capacitor

Ah, I see. But it's not significantly higher than other DRAMs, right? At least last I checked the difference wasn't that big.

I believe that data published by people peddling embedded dram ip is their "best case scenario" with still significant alteration to manufacturing process

While true, the same math holds for 22 nm^2 (484) to 14 nm^2 (196).

Real world gains will never be as high as the math suggests, as you get into leakage currents etc.

Sure, I never meant to imply that previous process steps were much smaller, just that this one is still formidable in its own right. Real world gains will not be 100% but they're a very large fraction of that. Obviously any technological advance in a mature industry is going to show reduced return on investment at some point, it's rather surprising that the ROI on these process shrinks is still worth it given that we are now well beyond what was thought to be possible not all that long ago.

Yeah, so the node names now apparently refer to the "smallest feature size", which is some random thing on the M0 metal layer. Source - from a former Intel engineer for more than a decade

So not like when games consoles used to advertise how many "bits" they had: take whatever has the widest bus and advertise that as the number of "bits" or use tricks like the Atari Jaguar: 2x 32bit cpu's = 64bit, right? RIGHT?

That's how Intel define it; other fabs have their own definitions.

Reply on news.ycombinator.com