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For that matter, what is wrong with MIPS?

Open ISA and a full open source implementation by MIPS themselves?

MIPS has numerous defects. There is a legacy wart in the form of a delay slot that doesn't match modern pipelines; this causes all sorts of annoyances. The MMU doesn't use a hardware-walked tree, cutting into performance with cache misses and even code execution. Forming addresses requires a silly number of instructions, or alternately you give up and just load relative to a specific register. The architecture fails to specify a coherent fully physical cache, causing all sorts of performance-killing trouble in OS kernels. There are wasted bits, commonly in the "shamt" field. The "hi" and "lo" registers interfere with scheduling multiplication and division.

Are you familiar with the newer mips revisions?

They have been modernizing the architecture during the last 10 years.

I don't know as I don't have enough knowledge about the matter. I'm asking because on Wikipedia and in videos about jcore (which uses SuperH) it is touted as a nice ISA:

> High code density compared to other 32-bit RISC ISAs such as ARM or MIPS[8] important for cache and memory bandwidth performance.

Fair enough.

For the sake of completeness, it should be mentioned that arm, mips and riscv also have 16-bit ISA extensions to achieve better density.

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