Sandy Bridge on up have two AVX units per core and as you mentioned Knights Landing does as well, so I don't think it is a given that this will only have one per core. One AVX-512 unit when other chips already have two 256 bit AVX units doesn't seem like much of a leap.

> A couple of assumptions: > - We're talking double precision FLOPs

Double precision is not what is typically used to measure FLOPs.

> - We can theoretically do 16 double precision FLOPs per cycle

One AVX-512 lane would be able to work with 16 FLOPS or 32 if you count FMA (which I think is silly, but that's what Intel will do). Two AVX-512 lanes would double that, but one thing to remember is that Intel's chips don't run at their full clock speed when using their SIMD lanes to their fullest.

All of this is to say that I would guess the base clock speed could be lower, but it is likely to be much lower while filling the SIMD units.