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32 full width vector ALUs running at 3.5 GHz is probably not realistic. I think that it is running around 2GHz at most [1]. The trick is that FMAs are normally counted as two FLOP.

[1] (* (/ 512 64) 2 2 18 2 1000 1000 1000) = 1152000000000 FLOPS (512 unit over 64 bits double) times 2 for FMA times two units, over 18 cores at 2 GHz)

edit: the 10 core part has a base clock of 3.3GHz. The 18 core part will probably be in the 2.5 range at best (the best 18 core Broadwell I can find runs at 2.3, but it is a dual socket part). Running in full AVX512 mode will probably downclock the cpu further.

Yes this sounds more probable.

> The 18 core part will probably be in the 2.5 range at best (the best 18 core Broadwell I can find runs at 2.3, but it is a dual socket part). Running in full AVX512 mode will probably downclock the cpu further.

Indeed, the 2.2-2.3/2.7-2.8 GHz (base/boost) of the >18C E5-269X v4 CPUs is the non-AVX instruction clock. With AVX the throttling these drop by 300-400 MHz [1] and I expect the skylake chips to behave very similarly. In fact I would not be surprised if on average 512-bit AVX2 required more throttling than 256-bit.

[1] https://www.microway.com/knowledge-center-articles/detailed-...

But current Intel CPUs already have dual AVX2 units; if it's just one AVX512, there aren't going to really be any gains (though some of the new instructions would be useful).

Knight's Landing has two per core, but they are pretty weak in IPC, so even if Skylake also had two they'd still maintain differentiation.

Although even with one unit, having 2x the registers of 2x the width means you can fit a significantly larger working set without spilling to cache...

So there still would be benefit even if it's just one unit.

you also get generalized predication which is nice for ease of vectorization. Still, it is very likely that these CPUs have two full vector ALUs per core.

If I remember correctly, first generation AVX (Sandy Bridge) does not actually have AVX unit, it just execute equivalent SSE instruction two times instead. So it is not surprising if the dual AVX2 units also double as AVX512 unit here.

>> We expect it to be enabled on day one, although I have a suspicion there may be a BIOS flag that needs enabling in order to use it.

>This seems odd.

When AES support was first introduced it was incredibly difficult to find a motherboard that would support it from the box, it almost universally required a BIOS update.

Even later on BIOS got it wrong from time to time.

Sandy Bridge on up have two AVX units per core and as you mentioned Knights Landing does as well, so I don't think it is a given that this will only have one per core. One AVX-512 unit when other chips already have two 256 bit AVX units doesn't seem like much of a leap.

> A couple of assumptions: > - We're talking double precision FLOPs

Double precision is not what is typically used to measure FLOPs.

> - We can theoretically do 16 double precision FLOPs per cycle

One AVX-512 lane would be able to work with 16 FLOPS or 32 if you count FMA (which I think is silly, but that's what Intel will do). Two AVX-512 lanes would double that, but one thing to remember is that Intel's chips don't run at their full clock speed when using their SIMD lanes to their fullest.

All of this is to say that I would guess the base clock speed could be lower, but it is likely to be much lower while filling the SIMD units.

RE: double counting FMA. I don't think it's that silly.

If you didn't count that operation as two different floating point operations you suddenly lose the ability to compare FMA chips to non-FMA chips. It's much simpler to just count it as two.

512 bit registers fit 8 doubles and 16 floats, and it's not as simple as 16 flops per cycle. They are probably counting fused multiply adds which are usually the highest flop/cycle instruction.

If an FMA can be done in one cycle, then we have 18 x 32 = 576 flops, so if it's clocked at e.g. 2.0 ghz, peak performance would be ~1.1 Tflops.

Edit: I see someone wrote exactly 8 hours before..