If you had a "sufficiently smart compiler" you wouldn't need register renaming and instruction reordering, but such a compiler has consistently failed to appear. That's a big part of the whole Itanium fiasco.

If you want your CPU to run fast, you have to pipeline instructions and you need caches that can run at full CPU speed. It's easy to design a CPU without all the complexity, but it will be slow. No one knows how to do both simple and fast. It's probably impossible.