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As I was trained in Verilog and know little about VHDL, to be honest, I'm not quite sure why "code" is inappropriate.

But thinking about your(blasdel's and gte910h's) comments, I'm beginning to see how error-checking can and should be different for FPGA development.

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Because neither Verilog nor VHDL is code. HDL is a slightly handwavey description of the graph of a machine, not something that runs on a machine.

You have wires, not variables: real physical wires connecting gates and LUTs. Since you're dealing with real-world electrical current, each wire can be in one of four binary states (null, low, high, grey). There's no concept of time beyond the speed of light itself unless you deliberately bind a clock line from the outside to a wire.

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