Looks like a good project, a nice change from doing everything in HDL.
Isn't the circuit layout going to get quite large however? How are you going to organize it? E.g. does Logisim have hierarchical views or sub-components?
Isn't the circuit layout going to get quite large however? How are you going to organize it? E.g. does Logisim have hierarchical views or sub-components?
I am a further into the development of the CPU then I show in the blog, as such I do have ISA already, but it's constantly changing. The control bus though, is final I think.