There are some open source toolchains, such as Yosys [1] and Qflow [2] for synthesising Verilog into ASIC designs that can be fabricated. And with multi-project wafer fab services like CMP and MOSIS, fabrication can be had in the tens of thousands of dollars for a few hundred ICs. So things aren't quite as bad as you make it sound, but it's still a big investment and requires a lot of fairly niche skills and experience.

1. http://www.clifford.at/yosys/ 2. http://opencircuitdesign.com/qflow/