And also, as long as you use only two layers, which given how cheap are 4-layer boards from china is pretty significant limitation, especially for project of this kind.
This: http://www.embedded.com/electronics-blogs/break-points/44311... shows a TTL era computer board, which seems to cram in about 300 packages in 15x15 inches.
Assuming each package is at most 500 gate (medium-scale integration) with 5 transistors/gate, that's 2,500 transistors per package.
So in 225 square inches we'd get 300*2500 = 750,000 transistors.
The Core i7 "only" has 731 million, which converts to 975 of those giant boards. But each such board is just 0.15 square meters, and in 100x50 meters we can fit more than 33,000 of them, for billions of transistors.
Of course, the max clock would not be very impressive at this scale. :)