In that class students design and implement in logic gate level simulator a 32-bit RISC CPU.
Is that an euphemism to avoid saying "MIPS"? ;-)
One way to really cut down on hardware (and speed) is to use a bit-serial design, as found on some minicomputers in the 70s. Memory elements like registers still need the full width, but by processing only 1 bit at a time, many of the other components in the datapath can be reduced by a factor of 32. You can also get left and right shifts for "free" since that's intrinsic in the design. Another strategy is to use microcode to break down instructions even further, e.g. reuse the ALU to do address calculations and incrementing the instruction pointer.