I took the MITx MOOC version of MIT's 6.004 (Computation Structures) class. In that class students design and implement in logic gate level simulator a 32-bit RISC CPU.

I was going to try to build it out of 74' series logic as a summer project last summer. Then I did a count of the gates I was using. In the following, a number after a gate type means the number of inputs. My gate count:

  295 AND2
    8 AND3
    3 NOR2
    4 OR2
   96 OR3
   20 OR4
  226 XOR2
    6 NOT
  563 MUX2
  161 MUX4
   32 D FLIP FLOPS

I'm not including memory for the registers. I would probably not have tried to make that out of 74' series logic.

In terms of chips, it is something like

  140 4xMUX2
   75 4xAND2
   81 2xMUX2
   55 4xXOR2

plus a few more.

The project pretty much died at that point.

I could cut a lot of those out by moving some functions from hardware to software. My design includes a shifter than can left or right, logical or arithmetic shift 1 to 32 bits in one cycle. 353 of the MUX2s are involved in that.

I could take that out, add a much simpler unit that can only do logical right shift by 1, add a new shift instruction that uses that simpler shifter, and make the current shift instruction into illegal instructions. They would then trap, and the illegal instruction handler could emulate the missing instructions.

Still too many chips after that, though.

I may still build it someday, but rather than making it out of real chips I'll use it as an excuse to learn about FPGAs.

If any of this seems interesting, I highly recommend 6.004 at MITx.