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Sure, I just meant that RISC-V being permissively licensed with in-depth documentation available will ease formally verifying implementations of it, and also encourage open-source implementations.

On the minion cores: that sounds quite interesting and I'm reading the paper now. Are they very different from e.g. the USB and network chips on the RPi, aside from having open firmware?

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For the initial iteration of minion cores, think of them as being an openly documented boot core and a way of implementing low-speed I/O in software (with some extra hardware support for things that would be dumb to do in software, e.g. shifting out a register). The initial target is SPI, I2C, I2S etc. Over the longer term, we are interested in using modified RISC-V cores for high-speed I/O and in general increasing the flexibility of a typical SoC design.

Are the minion cores comparable to the PRU's in the Beaglebone?

Our initial use case (real-time and programmable I/O) is very similar, so yes.

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