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Comment by cryptarch | Hacker News Reader

I'll take a fully open-source computing device with Core2Duo-like performance any day, especially if the CPU is open source too. I'm just hoping it won't have any firmware blobs.

Would this being built on RISC-V help with getting a formal CPU spec?

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RISC-V is an open specification that can be implemented by proprietary and open source efforts alike. This means there's nothing stopping someone else doing a RISC-V SoC that, like most current commercial cores, has documentation "protected" by an NDA and inaccessible to most users.

As a fully open source effort, we of course want every aspect of the chip to be fully documented and auditable. It's useful to have something like a dedicated core to handle initial boot, but it's not useful to keep that core completely undocumented (e.g. the Intel Management Engine). Our answer there is what we term 'minion cores' (http://www.lowrisc.org/downloads/lowRISC-memo-2014-001.pdf), microcontroller-class cores to handle these sort of tasks. These are fully documented, open source, and implement the RISC-V ISA.

As for formal specifications, there has been some work on specifying the RISC-V ISA using L3 https://github.com/SRI-CSL/l3riscv. MIT have been working on a specifying using their 'Kami' tool as well.

> someone else doing a RISC-V SoC that, ... , has documentation "protected" by an NDA and inaccessible to most users.

This is, as far as I understand, at least in software, the main difference between Free- and Open Source-software.

I wonder if there is some movement like the Free Software movement but Free Hardware instead.

Take a look at http://fossi-foundation.org/. Whatever terminology you're using, I think it's right to say lowRISC and FOSSi have a shared vision for free and open source designs that respect user freedom.

Open source as defined by the OSI describes something identical to free software as described by the FSF.

* "Free software" and "open source software" are two terms for the same thing: software released under licenses that guarantee a certain, specific set of freedoms.

https://opensource.org/faq#free-software

What you're describing may be what's sometimes called "shared source".

Sure, I just meant that RISC-V being permissively licensed with in-depth documentation available will ease formally verifying implementations of it, and also encourage open-source implementations.

On the minion cores: that sounds quite interesting and I'm reading the paper now. Are they very different from e.g. the USB and network chips on the RPi, aside from having open firmware?

For the initial iteration of minion cores, think of them as being an openly documented boot core and a way of implementing low-speed I/O in software (with some extra hardware support for things that would be dumb to do in software, e.g. shifting out a register). The initial target is SPI, I2C, I2S etc. Over the longer term, we are interested in using modified RISC-V cores for high-speed I/O and in general increasing the flexibility of a typical SoC design.

Are the minion cores comparable to the PRU's in the Beaglebone?

Our initial use case (real-time and programmable I/O) is very similar, so yes.

RISC-V is no guarantee that the CPU is open source. RISC-V is only an open source ISA. Implementations of it could be proprietary or open source. Some could have firmware blobs.

Some of the RISC-V ISA details are final and some are not. Check their website for the specs.

There is the Berkley Out of Order Machine BOOM https://github.com/ucb-bar/riscv-boom, its performance approaches those of modern intel processors in core mark, I think it would probably be possible to eventually match them.

Thanks for the plug, but just to clarify, while BOOM approaches the cycles/instruction of Intel's server cores, it does not approach their clock frequencies! Still, I'd say its competitive with the current mobile processor segment. =)

C2D perf is adequate for lots of things. What I'd like to see:

- AESNI - fine grained sleep states

If your priority is being 100% blob-free, not being completely open to chip makers, take a look at IBM POWER. There's even a workstation project: https://www.crowdsupply.com/raptor-computing-systems/talos-s...

>Core2Duo-like performance

so you expect someone brand new to start at iphone 6 level of performance? ....

Check out the BOOM RISC-V core. It's a superscalar out of order core from the UCB-BAR that claims similar coremark/Mhz to Arm Cortex-A15 in about half the area.

See page 43 - https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-W...

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