Hacker News Reader

Comment by QuantumRoar | Hacker News Reader

Well, they are quite tiny. A billion transistors fit into the area of your thumbnail. A typical wafer used for lithography has a diameter of 300mm. You can fit quite a few processors on such a wafer and you only have to expose once at each lithography step to create all of them.

View on HN

I have no idea how one can get a billion transistors to work. Even an extremely small failure rate can render it impossible.

Yes, it's an extremely technologically difficult process. That's why building a new fab cost billions[1].

1. https://en.wikipedia.org/wiki/Semiconductor_fabrication_plan...

I remember back in the 80s when engineers speculated that anything bigger than a 64K DRAM would be impossible because nobody could get that many transistors all working at the same time.

Technology is one challenge. I wonder what other kinds of scaling must take place to sustain such industries? Like, how do you scale learning, so that a single person or a small team is able to have a good overview plus detailed know-how on the these complex devices.

I remember Linus Torvalds mentioning, that while the 386 was a complex CPU, he was able to understand it on a sufficient level. But this time seems to be gone.

It's exactly like software: hierarchical design. You have a number of subsystems on a chip, each one of which has interfaces and resources requirements, the implementation of which is delegated down to teams and individuals or composed from pre-existing pieces.

DRAM is even "easier" because it's just a repeating grid pattern. Tuning the cell design is important for performance, as are the read sense amplifiers at the end of each row, but once the tuning is satisfactory you just get the software to make N copies.

Possibly the most overlooked part of the process is the bits that aren't either taught or written down but passed on in the oral culture of the engineers. Analog IC design is a lot more like this.

"how do you scale learning, so that a single person or a small team is able to have a good overview plus detailed know-how on the these complex devices."

I don't think that there is a single person to understand a modern, complex CPU and its production in full details. Take, for example, a datasheet of modern CPU/SoC -- it's thousands of pages of dense, technical information, and that's already a (comparatively high level) abstraction. As one professor told us in university: technology systems are getting more and more complex very fast, and soon (if not already) the biggest problem will be that noone fully understands how things/infrastructure, our society relies on, works. UML[1] and similar solutions alleviates this problem to some extend.

1. https://en.wikipedia.org/wiki/Unified_Modeling_Language

They, too, wondered that at some point. Even if you have an improbably low fail rate, the defects should break every single chip, right? Turns out, defects in manufacturing chips are not randomly distributed but very much localized. The chances of finding a defect next to another one is larger than finding one anywhere else. Thus, usually only a few chips are affected per wafer.

There are a lot of ways to achieve a higher yield rate, e.g. to increase operating voltages. Although most of the transistors produced could operate at lower voltages, thus being more energy efficient, they tend to apply a higher operating voltage just to be sure that the variances of the manufacturing don't impact the operation.

And there are a lot of other tricks, like identifying corner cases. What are the most affected paths through your ciruits? Or something like this one (don't know if it's still true): Intel never uses the first and last transistor of a row, since they always turn out worse than the others.

Then you start tweaking parameters for a few months and then you hopefully get a fab that can manufacture chips at a yield rate high enough to make a profit.

Current Intel production chips have feature sizes of 14nm, that is about 65 silicon atoms wide and they are hoping to release parts with 10nm early next year. Shrinking much below this size and you would think they would start to see reliability problems even if the chip was produced perfectly.

Articles announcing the end of Moore's law have been written since the early 2000's, but this time it really is different.

That's certainly true for conventional transistors. We may get a bit more mileage using carbon nanotubes or some exotic quantum technology.

Reply on news.ycombinator.com