Part 1: 50% applies, RAM controllers now part of the CPU, deprecating half of what’s written, also some CPUs have eDRAM. Part 2: almost completely applies. Part 3: 70% applies, hardware SLAT (Intel EPT / AMD RVI) deprecated what’s written about virtualization. Part 5: 90% applies. The rest of them — don’t know.

P.S. What’s I dislike most about the article, it fails to explain why L3 cache is 10-20 times slower than L1 cache, while they both made from SRAM.

From a quick look through, most of it. Modern x86 micro-architectures still use integrated memory controllers and ~3 level CPU caches.

All the timings are a little faster, the caches a little bigger, and the buses a little wider, but it's still basically the same stuff with different names.

I think its less important to know the exact numbers since those are a moving target but its more important to understand the orders of magnitude in difference from fastest to slowest and in between.

Things haven't changed much since the other day, so probably all of it.