Comment by lake99 | Hacker News Reader

Comment by lake99 | Hacker News Reader

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It's been a while since I studied or worked with these things, but I think your explanation is wrong. A transistor (BJT or FET, doesn't matter) dissipates very little in either cut-off region or saturation region (Rdson -- in FETs). It's in the active region that the transistor drops the most voltage across itself and has a fair amount of current flowing through it. I don't feel like doing the math right now, so I'll just cite something[1]. Anyway, when you're switching transistor from one state to the other, it invariably spends a little bit of time going through the active region. This is where it heats up the most. In the saturation stage, most of the voltage drop is across pull-up or pull-down resistors, so the V drop across the transistor is quite small. The higher the frequency, the more time the transistor spends in the active region, switching between states. This is why a given processor runs hotter a higher frequency.

But like I said, it's been a while since I worked in this field, so if someone knows better please correct me.

[1] http://www.satcure-focus.com/tutor/page4.htm

I prefer "oversimplified" :)

You're correct that there is more dissipation in the active region, but the Rdson is not negligable because the transistors are so small and the gate voltages so low (1.8V or less).

Switching does dissipate power based on switching speed. For "big" macroscopic FETs driving motors you have a separate gate driver amplifier to handle this. Within a chip, there's a tradeoff because driving a particular gate fast requires a bigger transistor to do the driving, which in turn requires a bigger transistor to drive it - so if you're not careful you spend a lot of area.

Transistor sizes are individually tuned during the design process (usually 99% algorithmically, 1% human intervention). There's a whole bunch of tunable design parameters.

I didn't discuss "leakage" either, so here's Intel on "high k metal gate" technology: http://www.intel.com/pressroom/kits/advancedtech/doodle/ref_...

(Basically, for big FETs we pretend that the resistance between gate and drain-source channel is infinite. For tiny ones it's surprisingly small and electrons can simply tunnel through your "insulator").

I think you underestimate the switching losses. The transistor gate is effectively a capacitor. To turn in on the voltage must be raised above some threshold, and it's this gate charge = CV with an energy of 0.5CV^2 that is important. Then when the switch is turned off, that gate charge is dumped to ground and the energy is lost. All of these losses are related in digital logic, as the gate charge comes from the conduction current through some other transistor. So you are correct, and the parent is also correct. Fin-FETs are interesting because they put gate material on 3 sides of the channel which allows them to switch on and off more completely, but that also increases the gate capacitance which means more current and power to switch it.

Well, you just further explained pjc50's first explanation. I don't see anyplace where you disagree.

Besides, CMOS ensures there is very little current going through the circuit when it isn't switching. What increases the differences between a fully cut or saturated transistor and a switching one.

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