The smallest transistor reported to date | Hacker News Reader

The smallest transistor reported to date

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If an atom is .1 - .5nm. That means the transistor wires are about 2-10 atoms thick. About what Richard Feynman predicted in his "plenty of room at the bottom". This is Amazing.

Is it possible to have a cube of 1nm transistors. Like a 100 million ^ 3. The cube would have size of 10cm w.d.h.

> Is it possible to have a cube of 1nm transistors. Like a 100 million ^ 3. The cube would have size of 10cm w.d.h.

Probably, but I suspect operating it would cause it to melt or explode :-) We could probably manufacturer 3D chips today (or more 3D than they are today), but from what I understand cooling them starts to become a major issue. (Not involved in chip design or manufacturing)

Yes, cooling would definitely be a problem.

Perhaps a design like the Menger Sponge could help with that.

https://en.m.wikipedia.org/wiki/Menger_sponge

A total newb/layman question incoming; what exactly is the process that generates heat in CPUs?

Are there any known/theoretical ways in which information be transmitted and processed at the atomic/subatomic/quantum level without generating any heat?

a) Resistance. Every switching action is effectively charging a small capacitor (the transistor gate) through a wire. The wire has nonzero resistance. It will also usually be travelling through the gate of one or more transistors, which have a nonzero resistance ('Rdson').

b) Theoretically, all computing that 'destroys' information (overwriting one register value with another) costs entropy, although we're nowhere near that level at the moment - orders of magnitude away.

'Reversible' computing would theoretically not incur that cost.

It's been a while since I studied or worked with these things, but I think your explanation is wrong. A transistor (BJT or FET, doesn't matter) dissipates very little in either cut-off region or saturation region (Rdson -- in FETs). It's in the active region that the transistor drops the most voltage across itself and has a fair amount of current flowing through it. I don't feel like doing the math right now, so I'll just cite something[1]. Anyway, when you're switching transistor from one state to the other, it invariably spends a little bit of time going through the active region. This is where it heats up the most. In the saturation stage, most of the voltage drop is across pull-up or pull-down resistors, so the V drop across the transistor is quite small. The higher the frequency, the more time the transistor spends in the active region, switching between states. This is why a given processor runs hotter a higher frequency.

But like I said, it's been a while since I worked in this field, so if someone knows better please correct me.

[1] http://www.satcure-focus.com/tutor/page4.htm

I prefer "oversimplified" :)

You're correct that there is more dissipation in the active region, but the Rdson is not negligable because the transistors are so small and the gate voltages so low (1.8V or less).

Switching does dissipate power based on switching speed. For "big" macroscopic FETs driving motors you have a separate gate driver amplifier to handle this. Within a chip, there's a tradeoff because driving a particular gate fast requires a bigger transistor to do the driving, which in turn requires a bigger transistor to drive it - so if you're not careful you spend a lot of area.

Transistor sizes are individually tuned during the design process (usually 99% algorithmically, 1% human intervention). There's a whole bunch of tunable design parameters.

I didn't discuss "leakage" either, so here's Intel on "high k metal gate" technology: http://www.intel.com/pressroom/kits/advancedtech/doodle/ref_...

(Basically, for big FETs we pretend that the resistance between gate and drain-source channel is infinite. For tiny ones it's surprisingly small and electrons can simply tunnel through your "insulator").

I think you underestimate the switching losses. The transistor gate is effectively a capacitor. To turn in on the voltage must be raised above some threshold, and it's this gate charge = CV with an energy of 0.5CV^2 that is important. Then when the switch is turned off, that gate charge is dumped to ground and the energy is lost. All of these losses are related in digital logic, as the gate charge comes from the conduction current through some other transistor. So you are correct, and the parent is also correct. Fin-FETs are interesting because they put gate material on 3 sides of the channel which allows them to switch on and off more completely, but that also increases the gate capacitance which means more current and power to switch it.

Well, you just further explained pjc50's first explanation. I don't see anyplace where you disagree.

Besides, CMOS ensures there is very little current going through the circuit when it isn't switching. What increases the differences between a fully cut or saturated transistor and a switching one.

Extending your final point.

The effort to explore reversible computation technology is driven by a desire to fully minimise the energy cost of computation regardless of architectural details. Substrate or ISA make no difference, reversible computation operates under different rules of physics from non reversible computation.

Quite a lot of quantum information theory stuff is involved so I'm going to stop elaborating since I'm merely a layman with more than average interest in the fascinating topic of reversible computation. Best anyone interested in learning further read more from experts who really know what they are saying.

b) how is that theorethical? To change the bit information the old state needs to be 'lost' or dissipated as heat into the surroundings. How is this connected to a level from which we are orders of magnitude away (in which direction?).

The GP means that the cost[0] is several orders of magnitude below the heat dissipation from resistance, and thus negligible.

[0]: https://en.wikipedia.org/wiki/Landauer%27s_principle

Ah ok.

Superconductivity is the other facet of the picture - it makes resistance effectively zero. Superconductivity usually needs very low temperatures (usually below the temperature that nitrogen is liquid).

For a CPU, you still need to address the transistors somehow. Chips aren't pure transistors, there are wires coming down from above, and that takes up a lot of space. As a result, vertical density doesn't scale as you might hope.

For example:

https://en.wikipedia.org/wiki/Integrated_circuit#/media/File...

I don't know if it's possible, but it's usually called "computronium".

I am curious how you arrived at the calculation that:

"That means the transistor wires are about 2-10 atoms thick"

Can you elaborate?

It's right in the article: this design uses a gate that's 1 nm thick. (1 ÷ .1) = 10.

Perhaps I'm guilty of falling for marketing definitions, but aren't we already down to 14nm rather than the 20nm the article suggests in the opening paragraph?

>They knew that the laws of physics had set a 5-nanometer threshold on the size of transistor gates among conventional semiconductors, about one-quarter the size of high-end 20-nanometer-gate transistors now on the market.

I think 14nm is the current smallest feature size in modern cpus. Like a resolution. A transistor is made up of multiple features.

This is correct. And many foundries will be manufacturing 7nm transistors in 2017-2018. So it seems like this article is a bit incorrect.

When they say that they are manufacturing a 7nm transistor it means the smallest feature is 7nm across. The gate size isn't always the smallest feature of a transistor; it typically is, but not always. And sometimes the larger features can be 4 to 5 times bigger, i.e a drain can be 40~50nm across because it connects to multiple other transistors or is part of a compound transistor. Transistors are inherently analog devices and so feature layout isn't as simple as "I need an XOR gate in this part of the circuit".

14 nm is just a name at this point, as discussed in this public available article:

"Between the ill-defined naming of new process nodes across the entire industry and Intel’s continuing lead in semiconductor manufacturing, Intel likes to point out how their manufacturing nodes compare to foundry competitors such as TSMC and the IBM alliance. Citing 3rd party journal articles for comparison, Intel claims that along with their typical lead in rolling out new nodes, as of the 14nm node they are going to have a multiple generation technical advantage. They expect that their 14nm node will offer significantly smaller feature sizes than competing 14nm nodes, allowing them to maintain consistent logic area scaling at a time when their competitors (i.e. TSMC) cannot." http://www.anandtech.com/show/8367/intels-14nm-technology-in...

Paper at http://science.sciencemag.org/content/354/6308/99 DOI: 10.1126/science.aah4698

It's paywalled, even though this was work done at a U.S. Government laboratory with tax funding. DOE has a 12 month "embargo" before the paper goes on line for free. There's a previous paper on line, though, which describes the process by which they get a stable one atom thick layer of molybdenum disulphide on a silicon substrate.[1] Another paper covers how they got a semiconductor junction made of molybdenum disulphide.[2] They've clearly been plugging away at this exotic area of semiconductor device physics for a while.

[1] http://www.osti.gov/pages/servlets/purl/1259305 [2] http://www.osti.gov/pages/biblio/1256052-mos2-heterojunction...

Appreciating all that, SciHub should provide access.

http://sci-hub.bz

> Because electrons flowing through MoS2 are heavier

Really?

What they mean is that they have less energy and thus less likely to tunnel between source and drain.

Not quite. They mean they have a higher effective mass, which is a solid-state physics quantity describing quasi-particles such as electrons and holes in a crystal. You are correct that high effective mass particles do not quantum tunnel as easily, though.

The correct word would be more energetic. Which measures as heavier on a current scale.

Short answer: https://en.wikipedia.org/wiki/Effective_mass_(solid-state_ph...

Long answer: It's necessary to use some math to explain this, but I'll try to skip it.

Let's talk about holes first, because it's easier to understand. In a semiconductor, the electrons can have only some values of energy. And sometimes you have a place where an electron is "missing". In a normal crystal you must find an electron there. But perhaps there is an impurity (an atom that is not the expected atom in the crystal) or perhaps another process, so you get an empty site where an electron should be. For some calculations, it's more easier to think about the missing electron than to think about all the other electrons that are there, so it's usual to call it a "hole". For many calculations, you can use the hole as a real particle, and get the correct result. (The physicist that work with crystal truly believe that they are real particles, and they will become slightly annoyed if you argue otherwise. :) ) The holes are some kind of weird particle that only can live inside a crystal, they can´t travel in empty space. https://en.wikipedia.org/wiki/Electron_hole

If you combine an electric and a magnetic field, then you can measure the charge of the particles that are traveling inside a semiconductor or crystal. The strange thing is that if you do this experiment with a semiconductor with many holes, then your experiment will show that there are positive particles traveling there, as if the hole were real and the lack of a negative electron produce positive hole. (It's possible to get the same result using the electrons and fermionic algebra, but the calculation is very complicated, it's much easier to get alone and think about holes.) https://en.wikipedia.org/wiki/Hall_effect

Now, what is the mass of a hole? Well, it's complicated. A hole is not only the lack of one electron, it's a perturbation in the nearby region caused by the missing electron. All the nearby electrons (and atoms?) move slightly to partially compensate the missing electron. (You need even some Fourier analysis for the details here.) But the mass of the hole is not equal to the mass of the missing electron, it's complicated, it's different and it's possible to measure it in an experiment. See again: https://en.wikipedia.org/wiki/Effective_mass_(solid-state_ph...

Back to "electrons". In a crystal, the electrons are not isolated electrons, you must think more in all the perturbation in the other electrons (and atoms?) that cause an electron moving inside the crystal. Imagine that each moving electron draft/repel/whatever a little the surrounding electrons. So in the experiments you can't measure the isolated electron inside the crystal, you measure an electrons with its tar ball. Perhaps it would be better to call it with a different name, to avoid the confusion with the isolated naked electron, let's call it electron-tar-ball. You can measure the mass of this electron-tar-ball as you can measure the mass of a hole. And the mass is not the mass of an isolated electron. See again the same article.

In the article, they say that the electron is heavier, they mean that the electron-tar-ball is heavier. The problem is that physicist call them "electrons", so it's confusing.

The "electron-tar-balls" real particles, they are as real as "holes". But they can only live inside crystals not in empty space. The difference is that in some experiments you can make the additional electron in the electron-tar-ball escape from the crystal and travel in vacuum, and when it's traveling in vacuum you get the usual mass.

IANAP but "heavier" and "more energetic" should be equivalent if E=mc². Of course, that's totally not how we use these words.

Quasi-particles, which includes electrons, in a crystal can have a wide range of effective masses depending on the crystal's band structure and the particle state.

I was both surprised and very confused at that wording.

Maybe the headline should be smallest transistor with manufacturing potential. See https://www.wired.com/2009/12/functional-molecular-transisto... and http://www.nrl.navy.mil/media/news-releases/2015/researchers...

Anyone with access to the full text know if they are reporting results on only one transistor or if they were able to fabricate and test several transistors?

With transistors getting smaller and smaller, do we better methods to dissipate heat? It seems like this is a major bottleneck.

Smaller transistors are able to operate at lower voltages which is typically why the TDP in watts have been dropping or remaining the same with more compute.

I think manufacturing is the big question mark. One is good as a proof of concept, but if you can't cram billions on a die then they can't compete. Hopefully they can work out manufacturing.

Producing the gates should be quite easy. The trouble is manufacturing and embedding the nanotube wires.

I thought I remembered something about circuits of this size being infeasible due to electrons hopping around?

That's specific to a material. The most commonly talked limits are even specific for MOS-FETs with a few specific insulators.

For alternative materials or designs, things change. Those people choose a material for exactly this property, it has a bigger resistance, but leaks less electrons.

There are also designs of transistors that switch on leaking current, never becoming a classical conductor. Those have negligible leaking when off.

Sounds like that was specific to transistors based on silicon

This technique is specifically about preventing that by using different materials.

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