Probably, but I suspect operating it would cause it to melt or explode :-) We could probably manufacturer 3D chips today (or more 3D than they are today), but from what I understand cooling them starts to become a major issue. (Not involved in chip design or manufacturing)
Perhaps a design like the Menger Sponge could help with that.
Are there any known/theoretical ways in which information be transmitted and processed at the atomic/subatomic/quantum level without generating any heat?
b) Theoretically, all computing that 'destroys' information (overwriting one register value with another) costs entropy, although we're nowhere near that level at the moment - orders of magnitude away.
'Reversible' computing would theoretically not incur that cost.
The effort to explore reversible computation technology is driven by a desire to fully minimise the energy cost of computation regardless of architectural details. Substrate or ISA make no difference, reversible computation operates under different rules of physics from non reversible computation.
Quite a lot of quantum information theory stuff is involved so I'm going to stop elaborating since I'm merely a layman with more than average interest in the fascinating topic of reversible computation. Best anyone interested in learning further read more from experts who really know what they are saying.
But like I said, it's been a while since I worked in this field, so if someone knows better please correct me.
You're correct that there is more dissipation in the active region, but the Rdson is not negligable because the transistors are so small and the gate voltages so low (1.8V or less).
Switching does dissipate power based on switching speed. For "big" macroscopic FETs driving motors you have a separate gate driver amplifier to handle this. Within a chip, there's a tradeoff because driving a particular gate fast requires a bigger transistor to do the driving, which in turn requires a bigger transistor to drive it - so if you're not careful you spend a lot of area.
Transistor sizes are individually tuned during the design process (usually 99% algorithmically, 1% human intervention). There's a whole bunch of tunable design parameters.
I didn't discuss "leakage" either, so here's Intel on "high k metal gate" technology: http://www.intel.com/pressroom/kits/advancedtech/doodle/ref_...
(Basically, for big FETs we pretend that the resistance between gate and drain-source channel is infinite. For tiny ones it's surprisingly small and electrons can simply tunnel through your "insulator").
Besides, CMOS ensures there is very little current going through the circuit when it isn't switching. What increases the differences between a fully cut or saturated transistor and a switching one.